Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)

Abstract

As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essential to model these leakage effects properly. Moreover, typical microprocessor caches are pipelined to keep up with the speed of the processor, and the effects of pipelining overhead need to be properly accounted for.In this paper, we present a detailed study of pipelined nanometer caches with detailed energy/power dissipation breakdowns showing where and how the power is dissipated within a nanometer cache. We explore a three-dimensional pipelined cache design space that includes cache size (16kB to 512kB), cache associativity (directmapped to 16-way) and process technology (90nm, 65nm, 45nm and 32nm).Among our findings, we show that cache bitline leakage is increasingly becoming the dominant cause of power dissipation in nanometer technology nodes. We show that subthreshold leakage is the main cause of static power dissipation, and that gate leakage is, surprisingly, not a significant contributor to total cache power, even for 32nm caches. We also show that accounting for cache pipelining overhead is necessary, as power dissipated by the pipeline elements is a significant part of cache power.

Clock gate on abort: Towards energy-efficient hardware Transactional Memory

“…In active mode, with the use of above mentioned techniques, the leakage power can be safely reduced to less than 20%. Recent product datasheets and publications [16], [3] also substantiate that leakage ratio can be assumed to be 20% in 65nm technology. When the processor is clock gated, apart from leakage, only the PLL is active.…”

Value-dependence of SRAM leakage in deca-nanometer technologies

“…We focus on I off as the primary contributor to leakage in nanometer caches [1]. Figure 1 shows a 6-transistor SRAM cell storing a 1 logic value.…”

“…A main cause behind such variations is the random dopant fluctuation (RDF) which differently affects even adjacent transistors and changes their V th . Since subthreshold leakage (I off , which is the dominant source of leakage in SRAM memories in nanometer technologies [1]) exponentially depends on V th , much bigger variations are observed in I off following the variations in V th . In the conventional 6-transistor SRAM cells, three of the transistors contribute to subthreshold leakage when storing a 1, and the other three contribute to leakage when storing a 0.…”

“…by reordering code blocks in a scratchpad memory), and/or (ii) by invalidating and refilling highly leaky SRAM cells with the less leaky value when going to standby mode. Since share of leakage in total power consumption of SRAM-based memories is increasing with technology scaling [1,2] and SRAM-based memories comprise the largest component of processor-based embedded systems (e.g. 70% of StrongARM [3]) and are among main sources of power consumption there [1], finding new opportunities for leakage reduction is important.…”

“…Since share of leakage in total power consumption of SRAM-based memories is increasing with technology scaling [1,2] and SRAM-based memories comprise the largest component of processor-based embedded systems (e.g. 70% of StrongARM [3]) and are among main sources of power consumption there [1], finding new opportunities for leakage reduction is important. Especially note that SRAM value-control can be done at system and software level without needing expensive changes at the circuit-level or manufacturing process.…”