Energy reduction for STT-RAM using early write termination

Zhou, Ping; Zhao, Bo; Yang, Jun; Zhang, Youtao

doi:10.1145/1687399.1687448

Cited by 288 publications

(140 citation statements)

References 15 publications

Supporting

Mentioning

137

Contrasting

Order By: Relevance

“…Novel management techniques have been proposed to mitigate the high write energy/latency of STT-MRAM based cache such as in [4], [5], [6]. Other works explored the performance improvement of STT-MRAM by reducing the retention time [7], [8].…”

Section: Introduction and Related Workmentioning

confidence: 99%

A novel SRAM — STT-MRAM hybrid cache implementation improving cache performance

Coi

Patrigeon

Senni

et al. 2017

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

View full text Add to dashboard Cite

Abstract-Memories are currently a real bottleneck to design high speed and energy-efficient systems-on-chip. A significant increase of the performance gap between processors and memories is observed. On the other hand, an important proportion of total power is spent on memory systems due to the increasing trend of embedding volatile memory into systems-on-chip. For these reasons, STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) is seen as a promising alternative solution to traditional SRAM (Static Random Access Memory) thanks to its negligible leakage current, high density, and non-volatility. Nevertheless, the strategy of the same footprint replacement is constrained by the high write energy/latency of STT-MRAM. This paper performs a fine-grained evaluation of the cache organization to propose a hybrid cache memory architecture including both SRAM and STT-MRAM technologies.

show abstract

Section: Introduction and Related Workmentioning

confidence: 99%

A novel SRAM — STT-MRAM hybrid cache implementation improving cache performance

Coi

Patrigeon

Senni

et al. 2017

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

View full text Add to dashboard Cite

show abstract

“…To reduce the power consumption by using a scheme of fixed-pulse-width write-scheme, several alternatives have been presented [7,13,14]. Ref.…”

Section: Introductionmentioning

confidence: 99%

“…Ref. [13] shut off the write-circuit when the old data (data written in the previous clock cycle) is same as the new data. If a data to be written is different from an old data, a conventional write-circuit with fixed-pulse width operates consuming a large writing current.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low-Power Write-Circuit with Status-Detection for STT-MRAM

Shin

Park³

2016

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-We report a STT-MRAM write-scheme, in which the length of the write-pulse is determined dynamically by sensing the status of MTJ cells. The proposed scheme can reduce the power consumption by eliminating unnecessary writing current after the switching has occurred. We also propose a reference cell design, which is optimized for the use in writecircuits. The performance of the proposed circuit was verified by SPICE level simulations of the circuit implemented in a 0.13 μm CMOS process.

show abstract

“…However, a major impediment to employ STT-RAM cells in on-chip caches has been their inferior write performance and energy-efficiency compared to conventional SRAM cells. Thus, the main focus of the previous studies is to mitigate an adverse impact of write operations in STT-RAM cells deployed for on-chip caches [1,2,3,4,5,6,7,8].…”

mentioning

confidence: 99%

A novel technique for technology-scalable STT-RAM based L1 instruction cache

Kong

2016

IEICE Electron. Express

View full text Add to dashboard Cite

STT-RAM is an emerging memory cell to construct on-chip memories or caches. However, in advanced process technology, it is known that STT-RAM cells are vulnerable to read disturbance. To employ STT-RAM cells in on-chip caches for better energy-and cost-efficiency, appropriate techniques to prevent or avoid read disturbance are essential. In this paper, we propose a novel architectural technique to enable an energy-and performance-efficient STT-RAM based L1 instruction caches for future process technologies. Our selective way access with a write line buffer adopts a sequential cache access between the MRU way and non-MRU way, reducing energy overhead from the data restoring after the read operation. In addition, the write line buffer hides a latency of currently pending or on-going write operations in L1 instruction caches, minimizing stalls in processor pipelines. Our proposed techniques improve performance per Watt of the STT-RAM based L1 instruction cache by 1.6X and 2.6X compared to the conventional SRAM-based cache (denoted as SRAM in this paper) and STT-RAM based cache with the naive data restoring (denoted as STTRAM_dr in this paper).

show abstract

Energy reduction for STT-RAM using early write termination

Cited by 288 publications

References 15 publications

A novel SRAM — STT-MRAM hybrid cache implementation improving cache performance

A novel SRAM — STT-MRAM hybrid cache implementation improving cache performance

Low-Power Write-Circuit with Status-Detection for STT-MRAM

A novel technique for technology-scalable STT-RAM based L1 instruction cache

Contact Info

Product

Resources

About