Engineered interface charges and traps in GaN MOSFETs providing high channel mobility and E-mode operation

Abstract

This review focuses on controlling interface charges and traps to obtain minimal channel resistance and stable enhancement-mode operation in GaN metal-oxide-semiconductor field-effect transistors. Interface traps reduce the free electron density and act as Coulomb scattering centers, thus reducing the channel mobility. Oxide traps cause instability of threshold voltage (V th) by trapping electrons or holes under gate bias. In addition, the V th is affected by the overall distribution of interface charges. The first key is a design of a bilayer structure to simultaneously obtain good insulating properties and interface properties. The other key is the optimization of post-deposition annealing to minimize oxide traps and interface fixed charges. Consequently, the gate structure of an AlSiO/AlN/p-type GaN has been designed. Reductions in V th as a result of polarization charges can be eliminated by using an m-plane trench channel, resulting in a channel mobility of 150 cm2V–1s–1 and V th of 1.3 V.