Engineering an Indium Selenide van der Waals Interface for Multilevel Charge Storage

Abstract

As the continuous miniaturization of floating-gate transistors approaches a physical limit, new innovations in device architectures, working principles, and device materials are in high demand. This study demonstrated a nonvolatile memory structure with multilevel data storage that features a van der Waals gate architecture made up of a partially oxidized surface layer/indium selenide (InSe) van der Waals interface. The key functionality of this proof-of-concept device is provided through the generation of charge-trapping sites via an indirect oxygen plasma treatment on the InSe surface layer. In contrast to floating-gate nonvolatile memory, these sites have the ability to retain charge without the help of a gate dielectric. Together with the layered structure, the surface layer with charge-trapping sites facilitates continual electrostatic doping in the underlying InSe layers. The van der Waals gating effect is further supported by trapped charge-induced core-level energy shifts and relative work function variations obtained from operando scanning X-ray photoelectron spectroscopy and Kelvin probe microscopy, respectively. On modulating the amount of electric field-induced trapped electrons by the electrostatic gate potential, eight distinct storage states remained over 3000 s. Moreover, the device exhibits a high current switching ratio of 106 within 11 cycles. The demonstrated characteristics suggest that the engineering of an InSe interface has potential applications for nonvolatile memory.

Fast, Multi‐Bit, and Vis‐Infrared Broadband Nonvolatile Optoelectronic Memory with MoS2/2D‐Perovskite Van der Waals Heterojunction

“…The memory response of the MoS 2 /2D-RPP heterojunction can still be observed, indicating that the device can achieve a fast write speed of 20 µs. Such fast write speeds are already better than most of the 2D-based memory reported (Figure 2e; Table S1, Supporting Information), [6,9,16,19,[25][26][27][28][29][30][31][32][33][34] indicating that 2D-RPP/ MoS 2 has great promise in realizing fast storage applications. As an indicator of non-volatile memory, data retention is essential.…”

Energy Barrier at Indium/Indium Selenide Nanosheet Interfaces: Implications of Metal-to-Insulator Transition for Field-Effect Transistor Modeling

“…Thermal evaporation using the shadow mask technique was used to fabricate two In/Au electrodes (40/50 nm). The detailed InSe crystal growth and FET device fabrication process have been described in our previous work. ,, An optical microscopy image of InSe FET device is given in the Supporting Information (Figure S3). Transfer ( I DS – V G ) measurements under constant source-drain voltage ( V DS = 0.5 V) acquired at various temperatures indicated a crossover from the insulator to the metal phase with increasing back-gate voltages.…”

“…Among 2D materials, layered indium selenide (InSe) is of considerable interest for electronic and optoelectronic applications [e.g., photodectectors and high-performance field-effect transistors (FETs)] due to its low effective electron mass ( m * = 0.143 m 0 ), high electron carrier mobility (cm 2 V –1 s –1 ) (due to weak electron–phonon scattering), and high density of states at the top of the valence band. − Moreover, theoretical reports predict that its band structure can be modified by adjusting the strength of interlayer coupling between two adjacent layers, allowing for properties distinct from the parent crystal . For example, the band gap of the InSe bilayer can be tuned by adjusting the stacking angles to vary the interlayer distance .…”

Properties, Synthesis, and Device Applications of 2D Layered InSe

“…2D materials InSe, with a clear surface, ultrahigh electronic mobility, and low energy consumption operation, is suitable for reliable in memory and synapse implementation. [40,238,239] Our group experimentally reported the memory and artificial synaptic device based on InSe flakes. [39] We found a native thin oxide layer at the bottom surface of the InSe channel formed in the air can serve as a charge trapping enhancement layer, enlarged the hysteresis window of InSe FET.…”