Engineering Change Order for Combinational and Sequential Design Rectification

Jiang, Jie-Hong R.; Кравец, В. В.; Lee, Nian-Ze

doi:10.23919/date48585.2020.9116504

Cited by 11 publications

(2 citation statements)

References 39 publications

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“…Subsequently, an Engineering Change Order (ECO) routing stage is executed. ECO routing becomes imperative when alterations or corrections are introduced to the design post-initial routing [10]. This iterative process ensures that any modifications made are seamlessly integrated into the existing layout, maintaining the overall integrity of the design while accommodating changes and rectifying errors effectively.…”

Section: F Routingmentioning

confidence: 99%

Comparative Implementation of PicoSoC System-on-Chip in X-Fab 180 nm CMOS Technology

Wuerdig,

H. Brendler,

Diniz

et al. 2024

JICS

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This paper presents the physical implementation of the PicoSoC System-on-Chip (SoC) using commercial EDA tools, to use it as a comparison source for future advances in open-source EDA tools for digital implementation flows. The PICORV32 is a simple and versatile microcontroller core that can be used for different applications (e.g., Internet of Things). The whole process entails logical and physical synthesis, design goals aspects, and reports by tools under different working conditions. The Logical and Physical synthesis of the PicoSoC for the X-Fab 180 nm node technology, presented in this work, relies on using the Cadence EDA tools. The microcontrollercore was fully synthesized with and without pads, resulting in a SoC that, including the pads, presents an estimated energy consumption of about 695.3 pJ per operation under nominal conditions.

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Section: F Routingmentioning

confidence: 99%

Comparative Implementation of PicoSoC System-on-Chip in X-Fab 180 nm CMOS Technology

Wuerdig,

H. Brendler,

Diniz

et al. 2024

JICS

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show abstract

“…The Path-RO implementation process can be automated by writing the engineering change order (ECO) commands [16], which is a method of directly modifying a postsynthesis design version at the gate level in the chip design flow [26]. This includes fixing errors found in the RTL (pre-synthesis) version of the design, optimizing the design, or updating the design with new customer requirements.…”

Section: Introductionmentioning

confidence: 99%

BPath-RO: A Performance- and Area-Efficient In Situ Delay Measurement Scheme for Digital IC

Li,

Liang,

Zhang

et al. 2023

Electronics

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Circuit delays are increasingly sensitive to process, voltage, temperature, and aging (PVTA) variations, severely impacting circuit performance. Accurate measurement of circuit delay is essential. However, the additional hardware structures for measuring circuit delay add to the critical path delay. To address this issue, this paper proposes a bypass-based ring oscillator (BPath-RO) that reduces the impact on the critical path delay by moving the added measurement control structures to the bypass. The proposed measurement scheme requires only two transistors inserted into the critical path, which is more conducive to engineering change order (ECO). Measurement simulation experiments were performed on representative critical paths of the ISCAS’89 s298 and ITC’99 b15 benchmark circuits. The experimental results show that, in comparison with the existing architectures, the Bpath-RO delay measurement scheme improves the circuit performance by an average of 13.81% (s298) and 3.47% (b15) and reduces the hardware overhead by up to 70% for each path.

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Effective Timing Closure Using Improved Engineering Change Order Techniques in SOC Design

Umadevi,

Venkatesh

2023

Wireless Pers Commun

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Engineering Change Order for Combinational and Sequential Design Rectification

Cited by 11 publications

References 39 publications

Comparative Implementation of PicoSoC System-on-Chip in X-Fab 180 nm CMOS Technology

Comparative Implementation of PicoSoC System-on-Chip in X-Fab 180 nm CMOS Technology

BPath-RO: A Performance- and Area-Efficient In Situ Delay Measurement Scheme for Digital IC

Effective Timing Closure Using Improved Engineering Change Order Techniques in SOC Design

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