2019
DOI: 10.1021/acsami.8b22362
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Engineering High-k/SiGe Interface with ALD Oxide for Selective GeOx Reduction

Abstract: Suppression of electronic defects induced by GeO x at the high-k gate oxide/SiGe interface is critical for implementation of high mobility SiGe channels in CMOS technology. Theoretical and experimental studies have shown that a low defect density interface can be formed with an SiO xrich interlayer on SiGe. Experimental studies in literature indicates better interface formation with Al 2 O 3 in contrast to HfO 2 on SiGe however the mechanism behind this is not well understood. In this study, the mechanism of f… Show more

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Cited by 19 publications
(27 citation statements)
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“…17 The 75% decrease in D it for ozone dosing into Al 2 O 3 /SiGe devices is consistent with both ozone and TMA dosing reducing interfacial GeO x but using different yet complementary chemical processes. The TMA reduces GeO x by gettering the oxygen from the SiGeO x interface to form Al 2 O 3 throughout the entire ALD process, 5 and it is hypothesized that the ozone promotes GeO x outdiffusion and eventually sublimation to form a Si-rich interface. Therefore, two distinct processes take place when ozone is inserted during Al 2 O 3 ALD: (1) D it reduction with ozone and (2) oxygen scavenging with remote oxide (TMA) gettering.…”
Section: ■ Methodsmentioning
confidence: 99%
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“…17 The 75% decrease in D it for ozone dosing into Al 2 O 3 /SiGe devices is consistent with both ozone and TMA dosing reducing interfacial GeO x but using different yet complementary chemical processes. The TMA reduces GeO x by gettering the oxygen from the SiGeO x interface to form Al 2 O 3 throughout the entire ALD process, 5 and it is hypothesized that the ozone promotes GeO x outdiffusion and eventually sublimation to form a Si-rich interface. Therefore, two distinct processes take place when ozone is inserted during Al 2 O 3 ALD: (1) D it reduction with ozone and (2) oxygen scavenging with remote oxide (TMA) gettering.…”
Section: ■ Methodsmentioning
confidence: 99%
“…As previously documented, multiple devices on the same wafer were probed to define standard D it error analysis and verify the repeatability . It is shown that the typical standard error is 3.9%; therefore, relative D it variation as low as 10% among different processing conditions can be reliably distinguished 5 .…”
Section: Interfacialmentioning
confidence: 97%
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