Enhanced 3D Implementation of an Arm<sup>®</sup> Cortex<sup>®</sup>-A Microprocessor

Xu, Xiaoqing; Bhargava, Mudit; Moore, Steve; Sinha, Saurabh; Cline, Brian

doi:10.1109/islped.2019.8824984

Cited by 10 publications

(3 citation statements)

References 19 publications

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“…This optimized SIMD execution approach, as shown in Fig. 3, balances hardware cost and execution e ciency, making it suitable for meeting the demands of embedded 3D rendering [7] . Due to the mop cache equipped with ARM, we can see that when the instruction footprint is up to 4KB, the mop cache can provide a throughput of 6 instructions per cycle.…”

Section: Embedded Simulation Systemmentioning

confidence: 99%

Research on Embedded 3D Simulation System for Collaborative Robots

Gao,

Geng,

et al. 2024

Preprint

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In this article designing an embedded simulation system for heavy collaborative robots. From the perspective of control system autonomy, controllability, and economy, the selection of ARM SOC for the embedded computer hardware, LCD driver for the upper computer, Linux operating system, and OpenCasCade for the 3D geometry engine were completed. The localization rate of the industrial robot control system was improved while ensuring performance requirements. Establish a kinematic mathematical model of the robot based on the DH parameter method, and obtain the kinematic equation of the robot's end effector. Simultaneously building an ARM Linux environment that can run simulation systems, using the 3D geometry engine OpenCasCade to load the robot standard STEP model file, using QtCreator to simulate and model the robot, and conducting instance simulations. By analyzing the motion of the robot through simulation results, the correctness of the kinematic algorithm was verified, which meets the expected design goals and provides a reliable basis for the research of collaborative robot trajectory planning and control。

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Section: Embedded Simulation Systemmentioning

confidence: 99%

Research on Embedded 3D Simulation System for Collaborative Robots

Gao,

Geng,

et al. 2024

Preprint

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“…Utilizing a novel 3D implementation flow, which allows cross-tier placement optimization, the 3D CPU implementation was able to achieve the same target frequency (3 GHz) as the 2D design. The critical steps of the flow are described in Figure 2 and more details are provided in [11], [12]. This highlights the importance of design-aware partitioning and cross-tier optimization to achieve high-performance 3D design.…”

Section: D Cpu Implementationmentioning

confidence: 99%

Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology

Mathur

Chao

Liu

et al. 2020

2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

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3D integration technologies are seeing widespread adoption in the semiconductor industry to offset the limitations and slowdown of two-dimensional scaling. High-density 3D integration techniques such as face-to-face wafer bonding with sub-10 µm pitch can enable new ways of designing SoCs using all 3 dimensions, like folding a microprocessor design across multiple 3D tiers. However, overlapping thermal hotspots can be a challenge in such 3D stacked designs due to a general increase in power density. In this work, we perform a thorough thermal simulation study on sign-off quality physical design implementation of a state-of-the-art, high-performance, out-oforder microprocessor on a 7nm process technology. The physical design of the microprocessor is partitioned and implemented in a 2-tier, 3D stacked configuration with logic blocks and memory instances in separate tiers (logic-over-memory 3D). The thermal simulation model was calibrated to temperature measurement data from a high-performance, CPU-based 2D SoC chip fabricated on the same 7nm process technology. Thermal profiles of different 3D configurations under various workload conditions are simulated and compared. We find that stacking microprocessor designs in 3D without considering thermal implications can result in maximum die temperature up to 12°C higher than their 2D counterparts under the worst-case power-indicative workload. This increase in temperature would reduce the amount of time for which a power-intensive workload can be run before throttling is required. However, logic-over-memory partitioned 3D CPU implementation can mitigate this temperature increase by half, which makes the temperature of the 3D design only 6°C higher than the 2D baseline. We conclude that using thermalaware design partitioning and improved cooling techniques can overcome the thermal challenges associated with 3D stacking. This is an accepted version of the IEEE published article presented at IEEE Electronic Components and Technology Conference (ECTC) 2020 http://www.ectc.net.

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“…As 3D technologies evolve, increasingly finer pitches of 3D connections become viable [18] [19]. This opens interesting possibilities for designers to partition and fold designs onto multiple tiers [20] [21]. Deep Neural Network (DNN) processing is heavy in computation and data movement [22].…”

Section: Introductionmentioning

confidence: 99%

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Mathur

Kumar

John

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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ML accelerators have a broad spectrum of usecases that pose different requirements on accelerator design for latency, energy, and area. In the case of systolic array-based ML accelerators, this puts different constraints on Processing Element (PE) array dimensions and SRAM buffer sizes. 3D integration packs more compute or memory in the same 2D footprint, which can be utilized to build more powerful or energyefficient accelerators. However, 3D also expands the design space of ML accelerators by additionally including different possible ways of partitioning the PE array and SRAM buffers among the vertical tiers. Moreover, the partitioning approach may also have different thermal implications. This work provides a systematic framework for performing system-level design space exploration of 3D systolic accelerators. Using this framework, different 3D-partitioned accelerator configurations are proposed and evaluated. The 3D-stacked accelerator designs are modeled using hybrid wafer bonding technique with a 1.44 µm pitch of 3D connection. Results show that different partitioning of the systolic array and SRAM buffers in a 4-tier 3D configuration can lead to either 1.1-3.9X latency reduction or 1-3X energy reduction compared to the baseline design of the same 2D area footprint. It is also shown that by carefully organizing the systolic array and SRAM tiers using logic over memory, the temperature rise with 3D across benchmarks can be limited to 6°C.

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Enhanced 3D Implementation of an Arm^® Cortex^®-A Microprocessor

Cited by 10 publications

References 19 publications

Research on Embedded 3D Simulation System for Collaborative Robots

Research on Embedded 3D Simulation System for Collaborative Robots

Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

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Enhanced 3D Implementation of an Arm® Cortex®-A Microprocessor

Cited by 10 publications

References 19 publications

Research on Embedded 3D Simulation System for Collaborative Robots

Research on Embedded 3D Simulation System for Collaborative Robots

Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Contact Info

Product

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Enhanced 3D Implementation of an Arm^® Cortex^®-A Microprocessor