Enhanced Degree Computationless Modified Euclid's Algorithm

Park, Jang W.; Baek, Jae Hyun; Sunwoo, Myung Hoon

doi:10.1109/apccas.2006.342412

Cited by 1 publication

(1 citation statement)

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“…they use different PEs for Q(x), R(x) and λ(x), µ(x). The same authors proposed the EDCME architecture in [10], which, based on the same concept, finishes in 2t − 1 cycles, as in our case.…”

Section: B Key Equation Solver (Kes) Unitmentioning

confidence: 87%

XG-PON optical network unit downstream FEC design based on truncated Reed-Solomon code

Georgis

Tzeranis

Reisis

et al. 2014

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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The XG-PON standard for Passive Optical Networks (PONs) requires the utilization of a Reed-Solomon block code at a 10Gbps downstream rate, dictating low latency and high throughput processing, no word interleaving and no stall between codewords. The current paper presents in detail a parallel architecture which decodes the RS(248,216) shortened code in the XG-PON ONT/ONU receiver. Based on a modified implementation of the Degree-Computationless Modified Euclidean (DCME) algorithm, the designed Key Equation Solver (KES) and its control unit allow for both solving the key equation and computing the number of the errors detected, in 31 clock cycles. Validating the proposed design on a Xilinx Kintex 7 FPGA and comparing to a pipelined serial DCME implementation reveals a reduction of 48% in the number of slices occupied and 6 times regarding the latency induced. Our implementation achieves a throughput of 16Gbps on the specified device thus meeting the XG-PON downstream FEC requirements with relatively low effort. The results could be adapted for a multitude of optical communication standards based on RS codes due to the 64-bit pipelined architecture and the FPGA-transparent HDL design

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Section: B Key Equation Solver (Kes) Unitmentioning

confidence: 87%