2016
DOI: 10.1016/j.cnsns.2015.11.010
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Enhanced dynamical response of derivative controlled third order phase locked loops

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Cited by 4 publications
(6 citation statements)
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“…Unlike several recent works where rigorous analyses are established for low order PLLs and PLLs with no integrators in the filters [10,12,16,34], the analysis presented in this paper is more general in the sense that not only it is applicable to both PLLs with analog mixer and XOR gate but also to PLLs without any order or type restriction. Unlike several recent works where rigorous analyses are established for low order PLLs and PLLs with no integrators in the filters [10,12,16,34], the analysis presented in this paper is more general in the sense that not only it is applicable to both PLLs with analog mixer and XOR gate but also to PLLs without any order or type restriction.…”
Section: Motivation and Contributionsmentioning
confidence: 99%
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“…Unlike several recent works where rigorous analyses are established for low order PLLs and PLLs with no integrators in the filters [10,12,16,34], the analysis presented in this paper is more general in the sense that not only it is applicable to both PLLs with analog mixer and XOR gate but also to PLLs without any order or type restriction. Unlike several recent works where rigorous analyses are established for low order PLLs and PLLs with no integrators in the filters [10,12,16,34], the analysis presented in this paper is more general in the sense that not only it is applicable to both PLLs with analog mixer and XOR gate but also to PLLs without any order or type restriction.…”
Section: Motivation and Contributionsmentioning
confidence: 99%
“…Both results in (b1) and (b2) are expressed in terms of convex LMIs, which are computationally tractable and more efficient than frequency-based methods. Unlike several recent works where rigorous analyses are established for low order PLLs and PLLs with no integrators in the filters [10,12,16,34], the analysis presented in this paper is more general in the sense that not only it is applicable to both PLLs with analog mixer and XOR gate but also to PLLs without any order or type restriction. In Section 4, several numerical examples are given where the result in (b1) is used to search for optimized value of K L in second and higher order Type-1 PLLs, and it is demonstrated that K L obtained can accurately estimate the corresponding lock-in range.…”
Section: Motivation and Contributionsmentioning
confidence: 99%
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