Enhanced Electrical Performance and Low Frequency Noise of In2O3 Thin-Film Transistors Using Al2O3/CeGdO
 x
 Bilayer Gate Dielectrics

Wang, Leini; He, Gang; Jiang, Shanshan; Wang, Wenhao; Xu, Xiaorong; Liu, Yanmei; Gao, Qian

doi:10.1109/ted.2022.3164632

Cited by 12 publications

(2 citation statements)

References 32 publications

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“…At low drain voltage, the carrier density distributes uniformly along the channel, implying that LFN can demonstrate the average defect density of the entire channel region. [ 48 ] Based On LFN measurements, it can be noted that DC HJ NFN TFTs conforms to the classical 1/ f noise theory in the fixed frequency range. [ 10,48,49 ] Observably, compared with I‐ON‐Z TFTs, the normalized drain current noise spectral density ( S ID / I DS 2 ) of I‐ON‐Z TFTs demonstrate a reduced trend, suggesting that the average trap density and interface trap density for I‐ON‐Z TFTs are reduced.…”

Section: Resultsmentioning

confidence: 86%

“…[ 48 ] Based On LFN measurements, it can be noted that DC HJ NFN TFTs conforms to the classical 1/ f noise theory in the fixed frequency range. [ 10,48,49 ] Observably, compared with I‐ON‐Z TFTs, the normalized drain current noise spectral density ( S ID / I DS 2 ) of I‐ON‐Z TFTs demonstrate a reduced trend, suggesting that the average trap density and interface trap density for I‐ON‐Z TFTs are reduced. To further confirm the main source of LFN of DC HJ TFTs, normalized S ID / I DS 2 properties were estimated and demonstrated in Figure 5g,h.…”

Section: Resultsmentioning

confidence: 87%

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Electrospun Stacked Dual‐Channel Transistors with High Electron Mobility Using a Planar Heterojunction Architecture

Jiang

et al. 2022

Adv Elect Materials

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Thin‐film transistors based on metal oxide semiconductors have become a mainstream technology for application in driving low‐cost backplanes of active matrix liquid crystal displays. Although significant progress has been made in traditional marketable devices based on physical vapor deposition derived metal oxides, it has still been hindered by low yield and poor compatibility. Fortunately, developing solution‐based 1D nanofiber networks to act as the fundamental building blocks for transistor has proven to be a simpler, higher‐throughput approach. However, oxide transistors based on such princesses suffer from degraded carrier mobility and operational instability, preventing the ability of such devices from replacing present polycrystalline Si technologies. Herein, it is shown that double channel heterojunction transistors with high electron mobility (>40 cm2 V−1 s−1) and operational stability can be achieved from electrospun double channels composed of In2O3 and ZnO layers. Adjusting the stacking order and the stacking density of In2O3 and ZnO layers can effectively optimize the interface electron trap, leading to the formation of 2D electron gas and the reduction of stress‐induced instability. These findings further elucidate the significant advance of electrospinning‐derived double channel heterojunction transistors toward practical applications for future low‐cost and high‐performance electronics.

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Section: Resultsmentioning

confidence: 86%

Section: Resultsmentioning

confidence: 87%

Electrospun Stacked Dual‐Channel Transistors with High Electron Mobility Using a Planar Heterojunction Architecture

Jiang

et al. 2022

Adv Elect Materials

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Design of different oxygen content and high performance bilayer In2O3 thin-film transistors at room temperature for flexible electronics

Zheng,

Abliz,

Wan

2025

Applied Surface Science

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Surface passivation of silicon substrate by ternary GaxCeyOz layers grown via combination of forming gas and oxygen at different temperatures

Kammutty Musliyarakath,

Cheong,

Quah

2024

Ceramics International

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Enhanced Electrical Performance and Low Frequency Noise of In₂O₃ Thin-Film Transistors Using Al₂O₃/CeGdO_x Bilayer Gate Dielectrics

Cited by 12 publications

References 32 publications

Electrospun Stacked Dual‐Channel Transistors with High Electron Mobility Using a Planar Heterojunction Architecture

Electrospun Stacked Dual‐Channel Transistors with High Electron Mobility Using a Planar Heterojunction Architecture

Design of different oxygen content and high performance bilayer In2O3 thin-film transistors at room temperature for flexible electronics

Surface passivation of silicon substrate by ternary GaxCeyOz layers grown via combination of forming gas and oxygen at different temperatures

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Enhanced Electrical Performance and Low Frequency Noise of In2O3 Thin-Film Transistors Using Al2O3/CeGdO x Bilayer Gate Dielectrics

Cited by 12 publications

References 32 publications

Electrospun Stacked Dual‐Channel Transistors with High Electron Mobility Using a Planar Heterojunction Architecture

Electrospun Stacked Dual‐Channel Transistors with High Electron Mobility Using a Planar Heterojunction Architecture

Design of different oxygen content and high performance bilayer In2O3 thin-film transistors at room temperature for flexible electronics

Surface passivation of silicon substrate by ternary GaxCeyOz layers grown via combination of forming gas and oxygen at different temperatures

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Product

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Enhanced Electrical Performance and Low Frequency Noise of In₂O₃ Thin-Film Transistors Using Al₂O₃/CeGdO_x Bilayer Gate Dielectrics