Enhanced Electrode Deposition for On-Chip Integrated Micro-Supercapacitors by Controlled Surface Roughening

Abstract

On-chip micro-supercapacitors (MSCs), integrated with energy harvesters, hold substantial promise for developing self-powered wireless sensor systems. However, MSCs have conventionally been manufactured through techniques incompatible with semiconductor fabrication technology, the most significant bottleneck being the electrode deposition technique. Utilization of spin-coating for electrode deposition has shown potential to deliver several complementary metal−oxide−semiconductor (CMOS)-compatible MSCs on a silicon substrate. Yet, their limited electrochemical performance and yield over the substrate have remained challenges obstructing their subsequent integration. We report a facile surface roughening technique for improving the wafer yield and the electrochemical performance of CMOS-compatible MSCs, specifically for reduced graphene oxide as an electrode material. A 4 nm iron layer is deposited and annealed on the wafer substrate to increase the roughness of the surface. In comparison to standard nonroughened MSCs, the increase in surface roughness leads to a 78% increased electrode thickness, 21% improvement in mass retention, 57% improvement in the uniformity of the spin-coated electrodes, and a high yield of 87% working devices on a 2″ silicon substrate. Furthermore, these improvements directly translate to higher capacitive performance with enhanced rate capability, energy, and power density. This technique brings us one step closer to fully integrable CMOS-compatible MSCs in self-powered systems for on-chip wireless sensor electronics.

Comparison of Thermally Grown Carbon Nanofiber‐Based and Reduced Graphene Oxide‐Based CMOS‐Compatible Microsupercapacitors

“…The recipe is discussed in further detail in corresponding literature. [ 14 ] The final fabricated devices are shown in Figure 1c,f. The wafer in 1(c) is a 2 in.…”

“…To be integrated into wafer‐scale fabrication of sensors for WSNs, MSCs must be compatible with complementary metal–oxide–semiconductor (CMOS) technology. There are several CMOS compatible techniques, for example, inkjet printing, [ 4–6 ] laser scribing, [ 7–9 ] chemical vapor deposition (CVD), [ 10–13 ] and spin coating [ 14–16 ] that have been used for MSC fabrication. Among these, the CVD and spin coating are among the most standard existing technologies used in a semiconductor foundry.…”

Alkyl‐Amino Functionalized Reduced‐Graphene‐Oxide–heptadecan‐9‐amine‐Based Spin‐Coated Microsupercapacitors for On‐Chip Low Power Electronics

“…The devices are fabricated using the processing scheme shown in Figure 1c. A silicon substrate is cleaned and the surface roughness is introduced as discussed in our previous research [8] (Figure 1c-i using Cr (2 nm) layer as a roughening surface instead of Fe (4 nm). The current collectors-Au/Ti are evaporated on the substrate surface through a well defined lift-off process (Figure 1c-ii.…”

“…[3] MSCs are capable of powering low power, high-density microelectronics through on-chip integration with energy harvesting sources such as solar or vibrational harvesters fabricated through an integrated circuit (IC) compatible process, as shown in Figure 1b. [4] Recently MSCs have been fabricated through CMOS compatible technologies such as spray coating, [5] laser scribing, [6] chemical vapor deposition, [7] spin coating, [8] and ink-jet printing. [9] Among these techniques, spin coating is one of the few techniques that can be considered versatile in terms of device microfabrication resolution, utilization of a variety of electrodes, and heterogeneous integration of electrodes as discussed in our previous publication.…”

Finger Number and Device Performance: A Case Study of Reduced Graphene Oxide Microsupercapacitors

“…[ 10 ] Such MSCs can be fabricated through several complementary metal–oxide–semiconductor (CMOS) compatible methods such as spin coating. [ 11–13 ] Moreover, the interdigital configuration allows for accurate control of the distance between electrodes, by leveraging standard microfabrication methods, and thus, the ion transport resistance in cells can be manipulated. However, compared to the conventional stack configuration, the interdigital design results in less areal energy density when a very thin electrode material layer is used, which is typically the case.…”