Enhanced ground bounce noise reduction in low leakage CMOS multiplier cell

Talwekar, R. H.; Jain, Nancy

doi:10.1109/rains.2016.7764404

Cited by 1 publication

(1 citation statement)

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“…Sreenivasulu and Rao [15] reported that transistor sizing techniques are adopted to reduce ground bounce noise. Based on literature [16], low leakage multiplier circuit is designed to control ground bounce noise using a stacked sleep transistor with a delayed select signal. Kumar et al [17] stated that multi-VDD level converter is used in PG technique to reduce the leakage current and ground bounce.…”

Section: Stacking Pg Approachmentioning

confidence: 99%

Low Dropout Based Noise Minimization of Active Mode Power Gated Circuit

Nath

Pradhan

2018

IJE

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The presence of package inductance induces large voltage fluctuation (bounce noise) on the power rail during power down to power up transition in the power gating circuit that may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in active mode. Noise for the architecture has also been analyzed. The effect of various noise minimization approaches for reducing power supply noise have been evaluated in power gating architecture. A new concept of noise minimization technique using Low Dropout Voltage Regulator has been proposed in this paper. The amount of charge in the internal nodes that passes through the sleep transistor during the wake-up transition has been controlled by the proposed noise minimization techniques. The Low Dropout Voltage Regulator is designed with a target of reducing bounce noise by minimizing voltage fluctuations on the power rail. Low noise active mode power gating architectures have been designed in Synopsys Custom Designer tool at iPDK 90nm technology. Saving of noise at the power supply rail has been observed up to 99%.

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Section: Stacking Pg Approachmentioning

confidence: 99%