Enhanced impurity-limited mobility in ultra-scaled Si nanowire junctionless field-effect transistors

Abstract

We examine the transport properties of heavily doped ultra-scaled Si junctionless nanowire field-effect transistors, by means of atomistic quantum transport simulations based on the sp3d5s∗ tight-binding model, the nonequilibrium Green's function formalism, and including electron-phonon scattering. Each individual doping atom is treated explicitly and its potential is determined by solving the Poisson equation. The impurity atoms are assumed to be aligned along a single line or to slightly vary from this well-ordered configuration. We find that the impurity-limited mobility enhances as the carrier concentration increases due to the screening effect. The mobility also improves with the doping concentration because closely placed impurities induce resonant tunneling states that positively affect the current magnitude. This behavior is found to persist even in the case of slight disorder.

(Invited) Large Mobility Modulation Due to Discrete Impurities in Nanowires

“…This is the case in highly doped source/drain regions in n-channel MOSFETs or n-channel Junctionless (JL) FETs. In fact, it is experimentally reported that the electron mobility in JL-FETs is enhanced as impurity density increases (20)(21). Our result is consistent with such experimental results and might provide a clue to understand the physical mechanism of such mobility enhancement.…”

“…It is shown that the impurity-limited resistance (mobility) could be modulated over three orders of magnitudes by varying the axial separation among the ionized impurities provided that the charge polarity of impurities is opposite to that of carriers. This finding could provide a clue to explain the recent experimental observations that the electron mobility in Junctionless-FETs (JL-FETs) is enhanced as the donor concentration becomes large (19)(20)(21).…”

Sidewall spacer layer engineering for improvement of analog/RF performance of nanoscale double-gate junctionless transistors

“…Moreover, to maintain super-steep doping profiles at the source-channel and channel-drain junctions of devices with a decananometer channel length becomes really challenging. In recent years junctionless transistors (JLTs) (Lee et al 2009;Colinge et al 2010;Ghosh et al 2012;Hur et al 2015;Wei et al 2014;Choi et al 2011;Baruah and Paily 2015;Chen et al 2013Chen et al , 2016Amin and Sarin 2015;Liu et al 2014;Yesayan et al 2016;Trevisoli et al 2016;Goh et al 2016;Ueda et al 2015;Kumar et al 2015;Roy and Biswas 2016) have been demonstrated in which no source-channel and channel-drain junctions exist. In contrast to inversion mode devices, such devices do not require any heavy source/drain implants.…”

Phase interference due to multiple impurities and space-average resistance in quasi-one-dimensional nanowires

“…[6][7][8][9] There are indeed several theoretical reports in which multiple impurities are introduced explicitly to evaluate the transport properties in the tight-binding NEGF and it has been demonstrated how the device characteristics could actually fluctuate, depending on the spatial configuration of impurities. [10][11][12][13] However, it is very difficult to extract the distinct effects of phase interference due to localized impurities among others from only such bruteforce simulations.…”