SPIE Proceedings
 2009
DOI: 10.1117/12.815413
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Enhanced layout optimization of sub-45nm standard: memory cells and its effects

Seung Weon Paek
1
,
Dae Hyun Jang
2
,
Joo Hyun Park
3
et al.
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Cited by 2 publications
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DfM at 28 nm and Beyond

Balasinski
1
2013
Design for Manufacturability
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DfM at 28 nm and Beyond

Balasinski
1
2013
Design for Manufacturability
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A sensitivity-aware methodology to improve cell layouts for DFM guidelines

Sundareswaran1,
Maziasz2,
Rozenfeld3
et al. 2011
2011 12th International Symposium on Quality Electronic Design
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