Enhanced Miller plateau characteristics of a 4H-SiC insulated-gate bipolar transistor in the presence of interface traps

Abstract

Miller plateau characteristics of a 4H-SiC insulated-gate bipolar transistor (IGBT) is investigated during a gate voltage turn-on under the presence of interface carrier traps at the MOSFET gate oxide. The plateau, which is observed in the device gate-emitter voltage, increased with respect to both height and length. The plateau height is mainly determined by the density increase of trap states, which also causes slow charging of the gate capacitance in the overlap region that results in a longer plateau length. The shallow trap states contribute mainly to the plateau increase. It is observed that the switching loss at turn-on can increase by more than 60% due mainly to the carrier traps at the shallow trap states.