“…In the meantime, fabrication limitations have been improved through techniques such as layout regularity [128] or double exposure [129], which are fundamental changes in design and fabrication methodologies rather than improving patterning resolutions. where τ d is delay, C L is load capacitance, V DD is supply voltage, I D is drain current, P dyn is dynamic power dissipation, P sc is short-circuit power dissipation, P leak is leakage power dissipation, sw is switching activity factor, V swing is voltage swing, f is clock frequency, t sc is the time short circuit power is dissipated, I peak is the peak current drawn during switching, and I leak is leakage current.…”