Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations

Zgheib, Grace; Ouaiss, Iyad

doi:10.1142/s0218126615500395

Cited by 3 publications

(4 citation statements)

References 14 publications

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“…This level is responsible for generating partial functions of outputs and IMFs. A block CPO1 generates SBFs (22) and (23). This block can be implemented using multiplexers created from basic LUTs and dedicated multiplexers of CLBs [17].…”

Section: Main Idea Of Proposed Methodsmentioning

confidence: 99%

“…The methods of functional decomposition are discussed in many books and papers, for example in [4,14,[19][20][21][22]. The FD is a very powerful tool used in the process of technology mapping [4].…”

Section: Related Workmentioning

confidence: 99%

“…Step 10. The table of CPO1 is a base for deriving SBFs (22) and (23). The table of the CM is used to derive SBF (24).…”

Section: Cs Pc(cs) St Fc(st)mentioning

confidence: 99%

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Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

2022

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A method is proposed that is focused on reducing the chip area occupied by logic elements creating the circuit of Mealy finite state machines (FSMs). The proposed method is aimed at FSM circuits implemented with internal resources of field-programmable gate arrays (FPGA). The required chip area is estimated by the number of look-up table (LUT) elements in a particular circuit. The method is based on mutual application of two methods of structural decomposition. The first of them is based on dividing the set of outputs and using unitary-maximum encoding of collections of FSM outputs. The second method is based on dividing the set of states by classes of compatible states. The optimization is achieved by replacing the maximum binary state codes by two-part codes proposed in this article. Each two-part state code consists of a code of a class including a particular state and a maximum binary code of this state inside a particular class. The proposed approach leads to three-level LUT-based Mealy FSM circuits. The first logic level generates three types of partial functions: unitary encoded outputs, variables encoding collections of outputs, and input memory functions. Each partial function is represented by a circuit including a single LUT. The LUTs from the second logic level generate final values of these functions. The LUTs from the third level implement outputs using collections of outputs. An example of synthesis applying the proposed method is discussed. The experiments were conducted using standard benchmark FSMs. Their results showed significant improving of the area occupied by an FSM circuit. The LUT count decreased on average by 9.49%. The positive side effect of the proposed method was increasing the value of the maximum operating frequency (on average, by 8.73%). The proposed method is advisable to use if a single-level LUT-based implementation of the FSM circuit is impossible.

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Section: Main Idea Of Proposed Methodsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

2022

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“…The heuristic achieves a 9% average reduction of the routing wires but the circuit delay is increased by 3%. Zgheib and Ouaiss [13] extended this heuristic with Boolean matching and decomposition techniques to achieve up to 24% reduction in routing wires. In contrast, our premapping approach discovers additional opportunities to use complete carry-chain logic by restructuring the gate-level description.…”

Section: Related Workmentioning

confidence: 99%

Improved carry chain mapping for the VTR flow

Petkovska

Zgheib

Novo

et al. 2015

2015 International Conference on Field Programmable Technology (FPT)

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Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-toRouting (VTR) CAD flow now enables modelling carry chains in FPGA architectures. However, one of the shortcomings of the existing flow lies in its inability to identify arithmetic operations when described as gate-level circuits. Moreover, the VTR flow squanders most of the LUTs preceding the chain logic. This paper focuses on these two problems and proposes preprocessing the circuit before technology mapping to allow for a more efficient use of carry chains. The first proposed method maps logic on the carry chains for circuits expressed using a gate-level description. On average, it identifies about 30% more meaningful full adders than the existing tool flow operating on the RTL descriptions. Area is thus improved by up to 15% with an average of 6% for almost no delay penalty. Secondly, we increase the use of the LUTs preceding the chain logic by a factor 2 on average. This reduces delay (up to 9%) and area (up to 2%), compared to the existing VTR flow. The new approach is independent of the specific carry-chain architecture and can be generically adapted to any FPGA with built-in hardened adders.

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Improving the Spatial Characteristics of Three-Level LUT-Based Mealy FSM Circuits

et al. 2023

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The main purpose of the method proposed in this article is to reduce the number of look-up-table (LUT) elements in logic circuits of sequential devices. The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called MPY FSMs based on two methods of structural decomposition (the replacement of inputs and encoding of output collections). The main idea is to use two types of state codes for implementing systems of partial Boolean functions. Some functions are based on maximum binary codes; other functions depend on extended state codes. The reduction in LUT counts is based on using the method of twofold state assignment. The proposed method makes it possible to obtain FPGA-based FSM circuits with four logic levels. Only one LUT is required to implement the circuit corresponding to any partial function. An example of FSM synthesis using the proposed method is shown. The results of the conducted experiments show that the proposed approach produces LUT-based FSM circuits with better area-temporal characteristics than for circuits produced using such methods as Auto and One-hot of Vivado, JEDI, and MPY FSMs. Compared to MPY FSMs, the values of LUT counts are improved. On average, this improvement is 8.98%, but the gain reaches 13.65% for fairly complex FSMs. The maximum operating frequency is slightly improved as compared with the circuits of MPY FSMs (up to 0.64%). For both LUT counts and frequency, the gain increases together with the growth for the numbers of FSM inputs, outputs and states.

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Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations

Cited by 3 publications

References 14 publications

Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs

Improved carry chain mapping for the VTR flow

Improving the Spatial Characteristics of Three-Level LUT-Based Mealy FSM Circuits

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