Enhancement-Mode GaAs MOSFETs With an $\hbox{In}_{0.3} \hbox{Ga}_{0.7}\hbox{As}$ Channel, a Mobility of Over 5000 $ \hbox{cm}^{2}/\hbox{V} \cdot \hbox{s}$, and Transconductance of Over 475 $\mu\hbox{S}/\mu\hbox{m}$

Detection of Ga suboxides and their impact on III-V passivation and Fermi-level pinning

“…It has previously been suggested that Ga 2 O deposition at the interface is necessary for a low defect density. 7,8 This is direct spectroscopic evidence of its presence at the III-V interface.…”

“…6͒ may be the most important of these species to control, and previous research has suggested that the deposition of a specific Ga suboxide may be necessary for a low defect density. 7,8 The determination of the specific bonding configurations that give rise to these interfacial trap defects has great implications for the electronics industry in the move away from Si-channel devices to those with higher mobility, such as GaAs and InGaAs.…”

In-situ characterization of Ga2O passivation of In0.53Ga0.47As prior to high-k dielectric atomic layer deposition

“…5 and 6) and Ge (Ref. 7) interfacial passivation layers (IPLs) and Gd containing gadolinium gallium oxide (GGO) interfacial oxides [8][9][10] have been employed in an attempt to control the chemical species present at the interface. Previous work has indicated the presence of Ga 2 O at the interface of devices showing improved capacitance-voltage (CV) and drain current-gate voltage (I d -V g ) characteristics on GaAs(100).…”

Charge trapping and reliability characteristics of ultra-thin HfYOx films on n-GaAs substrates

“…Furthermore, high-k dielectrics also provide an excellent opportunity for choosing alternative channel materials such as GaAs, InP, InGaAs for the requirement of ultra high-speed logic devices. Recently, GaAs is being considered as a potential channel material because of its augmented electron mobility, high breakdown strength and large band gap compared to Si [3][4][5][6] and successful integration of highk dielectrics on GaAs substrates draws significant attention to take advanced CMOS technology beyond 22 nm technology node [7][8][9][10][11][12]. However, reliability of ultra-thin high-k gate dielectrics have become more important, as high field applied to gate dielectric results in higher trap generation and oxide breakdown.…”