2024
DOI: 10.54097/s9j0f394
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Enhancement Of A 32-By-32-Bit Signed Digital Multiplier: A Multi-Dimensional Optimization Approach

Chenjia Cui,
Yunpeng Li,
Taoyujie Shang

Abstract: In the pursuit of enhanced performance in a 32-by-32-bit signed digital multiplier, optimizations were enacted on three critical fronts. Initial efforts focused on the integration of an advanced Booth encoding technique for the generation of three-bit control signals, meticulously crafted in the Verilog programming language. This approach, characterized by its restricted symbol expansion methodology, strategically curtails hardware resource expenditures, and diminishes power utilization during computational ta… Show more

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