Enhancement of capacitance benefit by drain offset structure in tunnel field-effect transistor circuit speed associated with tunneling probability increase

Abstract

The effect of a drain offset structure on the operation speed of a tunnel field-effect transistor (TFET) ring oscillator is investigated by technology computer-aided design (TCAD) simulation. We demonstrate that the reduction of gate-drain capacitance by the drain offset structure dramatically increases the operation speed of the ring oscillators. Interestingly, we find that this capacitance benefit to operation speed is enhanced by the increase in band-to-band tunneling probability. The "synergistic" speed enhancement by the drain offset structure and the tunneling rate increase will have promising application to the significant improvement of the operation speed of TFET circuits.

Steep switching less than 15 mV dec−1 in silicon-on-insulator tunnel FETs by a trimmed-gate structure

“…In this paper, we considered an N-type SOI TFET utilizing the drain-offset structure which prevents unnecessary off leak currents originating from BTBT from the source to the drain. [24][25][26] In the TG-TFET, the gate is trimmed to near the source edge. As a result, the channel region in which the gate electrostatic control is effective becomes extremely short, and long tunneling paths to the channel that normally appear in the standard-TFETs are cut off (see the yellow arrows in Fig.…”

Process and device integration for silicon tunnel FETs utilizing isoelectronic trap technology to enhance the ON current

“…The capacitance effect was considered by mixed-mode circuit simulations. 45) TFETs have the drain electrically connected to the channel. Thus, the gate-to-drain capacitance (C GD ) plays a key role in the operating speed.…”