Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems

Lee, Trong-Yen; Fan, Yang-Hsin; Cheng, Yu-Min; Tsai, Chia‐Chun; Hsiao, Rong-Shue

doi:10.1109/iihmsp.2007.4457483

Cited by 10 publications

(21 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The last two columns show the execution time of the hardware and software implementations. Lee et al [2007c] also provided detailed comparison of their methodology with another four approaches. The main problem is that the target architecture in Lee et al [2007c] has two processors and allows multi-processor partitioning while our target architecture is based on a single processor.…”

Section: Real-life Case Studymentioning

confidence: 99%

“…Lee et al [2007c] also provided detailed comparison of their methodology with another four approaches. The main problem is that the target architecture in Lee et al [2007c] has two processors and allows multi-processor partitioning while our target architecture is based on a single processor. A slight modification in our cost function is performed that allows up to two processors to run on the software part concurrently.…”

Section: Real-life Case Studymentioning

confidence: 99%

“…We carried out a comprehensive literature search in search for such case study. Lee et al [2007c] provided such details for a case study of the well-known Joint Picture Expert Group (JPEG) encoder system. The hardware implementation is written in "Verilog" description language, while the software is written in "C" language.…”

Section: Real-life Case Studymentioning

confidence: 99%

“…Table 1 shows measured data for the considered cost metrics of the system components. Including such table in Lee et al [2007c] allows us to compare directly our PSO search algorithm with the published ones without re-estimating the HW or SW costs of the design modules on our platform. Also, armed with this data, there is no need to re-implement the published algorithms or trying to obtain them from their authors.…”

Section: Real-life Case Studymentioning

confidence: 99%

“…In other words, we calculate the critical-path delay. In Lee et al [2007c], the results of four different algorithms were presented. However, for the sake brevity, details of such algorithms are beyond the scope of this chapter.…”

Section: Real-life Case Studymentioning

confidence: 99%

See 4 more Smart Citations

Particle Swarm Optimization for HW/SW Partitioning

Abdelhalim¹,

Habib²

2009

Particle Swarm Optimization

View full text Add to dashboard Cite

Section: Real-life Case Studymentioning

confidence: 99%

Section: Real-life Case Studymentioning

confidence: 99%

Section: Real-life Case Studymentioning

confidence: 99%

Section: Real-life Case Studymentioning

confidence: 99%

Section: Real-life Case Studymentioning

confidence: 99%

See 3 more Smart Citations

Particle Swarm Optimization for HW/SW Partitioning

Abdelhalim¹,

Habib²

2009

Particle Swarm Optimization

View full text Add to dashboard Cite

An integrated high-level hardware/software partitioning methodology

Abdelhalim

Habib

2011

Des Autom Embed Syst

View full text Add to dashboard Cite

Embedded systems are widely used in many sophisticated applications. To speed the time-to-market cycle, the hardware and software co-design has become one of the main methodologies in modern embedded systems. The most important challenge in the embedded system design is partitioning; i.e. deciding which modules of the system should be implemented in hardware and which ones in software. Finding an optimal partition is hard because of the large number and different characteristics of the modules that have to be considered.In this article, we develop a new high-level hardware/software partitioning methodology. Two novel features characterize this methodology. Firstly, the Particle Swarm Optimization (PSO) technique is introduced to the Hardware/Software partitioning field. Secondly, the hardware is modeled using two extreme implementations that bound different hardware scheduling alternatives. Our methodology further partitions the design into hardware and software modules at the early Control-Data Flow Graph (CDFG) level of the design; thanks to improved modeling techniques using intermediate-granularity functional modules. A new restarting technique is applied to PSO to avoid quick convergence. This technique is called Re-Excited PSO. Our numerical results prove the usefulness of the proposed technique.The target technology is Field Programmable Gate Arrays (FPGAs). We developed FPGA-based estimation techniques to evaluate the costs of implementing the design components. These costs are the area, delay, latency, and power consumption for both the hardware and software implementations. Hardware/software communication is also taken into consideration. This research is an extended version of IESS 2007 conference paper [5]. M.B. Abdelhalim ( ) College 20 M.B. Abdelhalim et al.The aforementioned methodology is embodied in an integrated CAD tool for hardware/software co-design. This tool accepts behavioral, un-timed, algorithmic-level, VHDL, design representation, and outputs a valid hardware/software partition and schedule for the design subject to a set of area/power/delay constraints. This tool is code named CUPSHOP for (Cairo University PSo-based Hardware/sOftware Partitioning tool). Finally, a JPEGencoder case study is used to validate and contrast our partitioning methodology against the prior-art methodologies.

show abstract

Evaluation of Partitioning Methods for Stream Applications on a Heterogeneous Multi-core Processor Simulator

Kai

Zhu

2008

2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing

View full text Add to dashboard Cite

Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems

Cited by 10 publications

References 2 publications

Particle Swarm Optimization for HW/SW Partitioning

Particle Swarm Optimization for HW/SW Partitioning

An integrated high-level hardware/software partitioning methodology

Evaluation of Partitioning Methods for Stream Applications on a Heterogeneous Multi-core Processor Simulator

Contact Info

Product

Resources

About