Enhancement of Parameters for 7T SRAM Cell in Nanometer Era

Abstract

As the technology scales down to 90nm and below, leakage current/ power is becoming one of the most critical concerns for low power applications. 40% or even higher percentage of the total power consumption is waste due to the leakage of the transistors. This paper compares the performance of two SRAM cell topologies, which includes the conventional 6T-cell and the 7T-cell.In particular the static noise margin (SNM) of each cell designed is examined. The conventional six transistors SRAM (6T) suffered from the external noise because they have direct paths through bit-line (BL) to their storage nodes. This paper proposes 7T SRAM cell which has no direct paths through bit-line (BL) to the data storage nodes and has higher endurance against external noise. The proposed 7T-cell is composed of two separate data access mechanisms; one is for the write one and another is for read. Here we examined the difference between the power consumption of both 6T and 7T cell and also find out which cell works better on low power.