Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Abstract

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth and data representation, through time-consuming Monte Carlo simulations. A prominent example of this simulation-based exploration process is the design of decoders for error correcting systems, such as the Low-Density Parity-Check (LDPC) codes adopted by modern communication standards, which involves thousands of Monte Carlo runs for each design point. Currently, high-performance computing offers a wide set of acceleration options that range from multicore CPUs to Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The exploitation of diverse target architectures is typically associated with developing multiple code versions, often using distinct programming paradigms. In this context, we evaluate the concept of retargeting a single OpenCL program to multiple platforms, thereby significantly reducing design time. A single OpenCL-based parallel kernel is used without modifications or code tuning on multicore CPUs, GPUs, and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL in order to introduce FPGAs as a potential platform to efficiently execute simulations coded in OpenCL. We use LDPC decoding simulations as a case study. Experimental results were obtained by testing a variety of regular and irregular LDPC codes that range from short/medium (e.g., 8,000 bit) to long length (e.g., 64,800 bit) DVB-S2 codes. We observe that, depending on the design parameters to be simulated, on the dimension and phase of the design, the GPU or FPGA may suit different purposes more conveniently, thus providing different acceleration factors over conventional multicore CPUs.

A comprehensive modeling approach for the task mapping problem in heterogeneous systems with dataflow processing units

“…21 Owaida et al discuss these differences in the context of designing OpenCL tasks for FPGAs. 22 Theodoridis et al designed a rather elaborated ILP for task mapping with special focus on hardware platforms. 23 They consider communication costs, data dependencies and resource conflicts.…”

Software-defined Radios: Architecture, state-of-the-art, and challenges

“…In addition, the authors in [109] report that GPUs are ten times faster than FPGAs with regards to FFT processing, while authors in [81] demonstrate that the power efficiency of FPGAs is always better than GPUs for matrix operations. Finally, authors in [110] compare GPPs, GPUs, and FPGAs through the implementation of LDPC decoders, and their results lead to the conclusion that GPUs and FPGAs perform better than GPPs. It is obvious from above studies that trade-offs are to be expected when a particular design methodology is adopted, hence careful analysis should be carried out beforehand.…”

Stacked Autoencoders Using Low-Power Accelerated Architectures for Object Recognition in Autonomous Systems

“…Currently supported in x86 and ARM CPUs, desktop and mobile GPUs, several APUs and FPGAs [9], the OpenCL programming framework provides the means to easily port an existing code into any compatible device [22], provided there is a software development kit (SDK) for that desired platform. The OpenCL framework links a host to one or more OpenCL devices, forming a single heterogeneous computational system [13].…”

“…In the end, the approach proposed in this work is capable of achieving classification performances comparable to the mid level of the Kaggle table [16], and above the accuracy obtained from processing raw pixels as the input data [17], while demanding power consumption levels ranging from 6.6 to 16 W, which makes them suitable for being incorporated in autonomous systems. Moreover, the proposed solution is scalable to future devices that expectedly should have more hardware resources and processing cores available [22], allowing more frames per second to be processed or more complex deep neural networks to be developed.…”