Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

Qureshi, Moinuddin K.; Karidis, John; Franceschini, Michele; Srinivasan, Vijayalakshmi; Lastras, Luis A.; Abali, Bülent

doi:10.1145/1669112.1669117

Cited by 668 publications

(422 citation statements)

References 13 publications

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“…Although researchers have suggested several ideas for dealing with PCM's endurance limitations, the question of whether they work as expected in commercial memories is still open. Using simulations, several studies have presented techniques that guarantee memory will not wear out before 7 years, which is more than the expected lifetime of DRAM [9], [10], [11], [12]. However, real devices could still be limited to shorter lifetimes, perhaps due to unforeseen effects in the fabrication of large scale memories or memory access patterns not covered by the simulations.…”

Section: B Pcm Writesmentioning

confidence: 99%

“…We use the endurance model of [9], [10] to compute the lifetime of PCM, assuming that a program is run back-to-back for as long as the memory lasts. Given the number of writes that a program makes during one execution, we can calculate how many times the program can be run before the memory expires.…”

Section: Energy and Endurance Modelsmentioning

confidence: 99%

“…Lee et al proposed multiple dirty bits per cache block to mask off unnecessary memory updates [19]. Qureshi et al examined a hybrid architecture that uses a DRAM cache to filter accesses to PCM and propose wear-leveling techniques to reduce writes [9], [10]. Ferreira et al propose page partitioning to reduce the size of the data that needs to be written back [11].…”

Section: Related Workmentioning

confidence: 99%

“…PCM cells endure only a limited number of writes, typically between 10 7 and 10 8 , before failing. Although PCM is more durable than other wearable memories, it still does not have enough endurance to be used in main memory without a wear-leveling or writefiltering mechanism [8], [9], [10], [11], [12]. The power and energy consumption of PCM writes is another major issue that provides several opportunities for improvement.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory

Bock

Childers

Melhem

et al. 2011

(Ieee Ispass) Ieee International Symposium on Performance Analysis of Systems and Software

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Abstract-Phase Change Memory (PCM) is an emerging technology that has been recently considered as a cost-effective and energy-efficient alternative to traditional DRAM main memory. Due to the high energy consumption of writes and limited number of write cycles, reducing the number of writes to PCM can result in considerable energy savings and endurance improvement. In this paper, we introduce the concept of useless write-backs, which occur when a dirty cache line that belongs to a dead memory region is evicted from the cache (a dead region is a memory location that is not used again by a program). Since the evicted data is not used again, the write-back can be safely avoided to improve endurance and energy consumption.This paper presents a limit study on the improvement that passing information to the memory system about useless writebacks has on the endurance and energy consumption of systems based on PCM main memory. We developed algorithms to measure the number of useless write-backs to PCM for three different types of memory regions and we present an energy model to determine the maximum energy savings that could potentially be achieved through such a scheme. Our results show that avoiding useless write-backs can save up to 19.8% of energy and improve endurance by up to 26.2%.

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Section: B Pcm Writesmentioning

confidence: 99%

Section: Energy and Endurance Modelsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory

Bock

Childers

Melhem

et al. 2011

(Ieee Ispass) Ieee International Symposium on Performance Analysis of Systems and Software

View full text Add to dashboard Cite

show abstract

“…However, PCM can endure about 10 7 -10 8 writes per cell [12] (even up to 10 12 by projection [7]), whereas flash memory can only endure about 10 5 -10 6 erase cycles per block [5]. Furthermore, PCM allows in-place update and does not have the erase-before-write constraint of flash memory, which further negatively and significantly impacts performance and lifespan of flash devices [11].…”

Section: Introductionmentioning

confidence: 99%

Wear-Aware Algorithms for PCM-Based Database Buffer Pools

Chen

et al. 2014

Web-Age Information Management

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Abstract. PCM can be used to overcome the capacity limit and energy issues of conventional DRAM-based main memory. This paper explores how the database buffer manager can deal with the write endurance problem, which is unique to PCM-based buffer pools and not considered by conventional buffer algorithms. We introduce a range of novel buffer algorithms addressing this problem, called wear-aware buffer algorithms, and study their behavior using trace-driven simulations.

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Storage Class Memory

Burr

Franzon

2014

Emerging Nanoelectronic Devices

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One challenge in computing systems is the need for new memory technologies that can improve overall performance. More and more frequently, the ability of a CPU to rapidly execute programs is being limited by the rate at which data can arrive at the processor. Unfortunately, scaling does not automatically solve this problem. One evolutionary solution has been to increase the size of cache memory and thus the floor space that SRAM occupies on a CPU chip. However, this trend eventually leads to a decrease of the net information throughput.While DRAM offers higher density than SRAM, auxiliary circuitry is required to maintain the stored data. True nonvolatility has conventionally required external storage media (e.g., magnetic Hard Disk Drives (HDDs), optical CDs, etc.), with access times that are slower than the volatile memory by many orders of magnitude. Solid-State Disks (SSDs) based on NAND Flash have recently offered nonvolatility at significantly lower latencies than HDDs, but are block-based, much slower to erase than to program, and offer fairly poor cycle endurance.The development of an electrically accessible nonvolatile memory with high speed, high density, and high endurance, referred to as "Storage Class Memory" or SCM, would initiate a revolution in computer architecture. By using CMOS-compatible fabrication technology scaled beyond the present limits of SRAM and FLASH, such a memory technology could enable breakthroughs in both stand-alone and embedded memory applications. This development could potentially provide a significant increase in information throughput beyond the benefits traditionally associated with scaling CMOS devices into the nanoscale.This chapter is structured as follows. Sections 25.2 and 25.3 motivate and define SCMs. Sections 25.4 through 25.6 discuss target specifications and potential device solutions. Sections 25.7 through 25.10 discuss architectural implications of SCMs and open issues related to architectural exploitation.

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Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

Cited by 668 publications

References 13 publications

Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory

Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory

Wear-Aware Algorithms for PCM-Based Database Buffer Pools

Storage Class Memory

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