Enhancing MPI performance using atomic pipelined message broadcast in a distributed memory MPSoC

Abstract

We propose a scheme for enhancing the MPI (Message Passing Interface) broadcast function performance with supporting hardware logic to reduce a number of synchronization processes which can be avoided on a distributed memory multiprocessor system on a chip (MPSoC). We accomplish this using the concept of atomic execution which facilitates full pipeline utilization. To validate our approach, we implemented a bus functional model with systemC and evaluated the results against various message data sizes and number of nodes. Evaluation results showed that performance improvement can be achieved by up to 230% over the precedent pipelined message broadcast method. Synthesis results with 4 processing nodes show that the extra hardware cost for the proposed atomic pipelined broadcast logic occupies only 2.4% of the entire area.

Efficient Pipelined Broadcast with Monitoring Processing Node Status on a Multi-Core Processor

“…The logic area of the modified MPE was 2288.1 (i.e., 9152.5 for four processing nodes) equivalent NAND gates. As described in [22], the logic area of the MPE supporting the initial transmission order change technique is 2108.4 (i.e., 8433.6 for four processing nodes) equivalent NAND gates. Compared to the previous MPE, the logic area of the modified MPE increased by approximately 8.5%.…”

“…As a preliminary study, the author presented the enhanced algorithm to overcome the disadvantage of pipelined broadcasting, which is called an atomic pipelined broadcast algorithm [22]. The term "Atomic" derives from the concept of an atomic transaction, where a transaction should be performed either in its entirety or not at all [42].…”