Enhancing On-die PDN for Optimal Use of Package PDN with Decoupling Capacitor

Hwang, Jisoo; Pak, Jun So; Yoon, Dooseok; Lee, Heeseok; Jeong, Jiyong; Heo, Yun Seok; Kim, Ilryong

doi:10.1109/ectc32696.2021.00288

Cited by 3 publications

(2 citation statements)

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“…Power delivery has become a huge technical bottleneck of hardware devices due to the continuously decreasing supply voltage margin along with the technology shrink of CMOS transistors [10]. interconnections of PCB, package and chip.…”

Section: B1 Domain Details Of Pdn and Decapmentioning

confidence: 99%

“…Decoupling capacitor (decap) is a hardware component that reduces noise along with the power distribution network (PDN) of hardware devices. With transistor scaling and continuously decreasing supply voltage margin [10], power noise has become a huge technical bottleneck of high-speed computing systems. Generally, the more decaps are placed, the more reliable the power supply is.…”

Section: Introductionmentioning

confidence: 99%

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Collaborative Distillation Meta Learning for Simulation Intensive Hardware Design

Kim¹,

Kim²,

Kim³

et al. 2022

Preprint

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This paper proposes a novel collaborative distillation meta learning (CDML) framework for simulation intensive hardware design problems. Deep reinforcement learning (DRL) has shown promising performance in various hardware design problems. However, previous works on DRL-based hardware design only dealt with problems with simplified objectives, which are not practical. In fact, the objective evaluation of real-world electrical performance through simulation is costly in terms of both time and computation, making DRL scheme involving extensive reward calculations not suitable. In this paper, we apply the CDML framework to decoupling capacitor placement problem (DPP), one of the significant simulation intensive hardware design problems. The CDML framework consists of a context-based meta learner and collaborative distillation scheme to produce a reusable solver. The context-based meta learner captures the location of probing port (i.e., target circuit block) and improves generalization capability. The collaborative distillation scheme with equivariant label transformation imposes the action-permutation (AP)-equivariant nature of placement problems, which not only improves sample efficiency but also improves generalization capability. Extensive experimental results verified that our CDML outperforms both neural baselines and iterative conventional design methods in terms of real-world objective, power integrity, with zero-shot transfer-ability.Preprint. Under review.

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Section: B1 Domain Details Of Pdn and Decapmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%