Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics

Rane, Ashay; Browne, James C.

doi:10.1145/2370816.2370838

Cited by 30 publications

(18 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Extrae uses binutils [22] to obtain human-readable source code references for the memory accesses. Dynamicallyallocated variables are identified by their allocation call-stack 4 while static variables are referenced by their given name.…”

Section: Tracementioning

confidence: 99%

“…Regarding the PEBS hardware infrastructure, the metrics associated to the memory samples depend on the processor fam- 4 The call-stack is captured using the backtrace() call from glibc.…”

Section: Tracementioning

confidence: 99%

“…1 Also known as heterogeneous or multi-tiered memory systems. Tools like EVOP [2], ADAMANT [3], MACPO [4] and Intel R Advisor [5] solely rely on instruction-level instrumentation to monitor the data object allocation and their respective accesses to advise the user about the most accessed variables and even their access patterns. These metrics are valuable to understand the application behavior, but the imposed overhead limit their relevance because they alter the application performance and generate a daunting amount of data for inproduction application runs, leading to long analysis times.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Automating the Application Data Placement in Hybrid Memory Systems

Servat

Peña

Llort

et al. 2017

2017 IEEE International Conference on Cluster Computing (CLUSTER)

View full text Add to dashboard Cite

Abstract-Multi-tiered memory systems, such as those based on Intel R Xeon Phi TM processors, are equipped with several memory tiers with different characteristics including, among others, capacity, access latency, bandwidth, energy consumption, and volatility. The proper distribution of the application data objects into the available memory layers is key to shorten the timeto-solution, but the way developers and end-users determine the most appropriate memory tier to place the application data objects has not been properly addressed to date.In this paper we present a novel methodology to build an extensible framework to automatically identify and place the application's most relevant memory objects into the Intel Xeon Phi fast on-package memory. Our proposal works on top of inproduction binaries by first exploring the application behavior and then substituting the dynamic memory allocations. This makes this proposal valuable even for end-users who do not have the possibility of modifying the application source code. We demonstrate the value of a framework based in our methodology for several relevant HPC applications using different allocation strategies to help end-users improve performance with minimal intervention. The results of our evaluation reveal that our proposal is able to identify the key objects to be promoted into fast on-package memory in order to optimize performance, leading to even surpassing hardware-based solutions.

show abstract

Section: Tracementioning

confidence: 99%

“…Regarding the PEBS hardware infrastructure, the metrics associated to the memory samples depend on the processor fam- 4 The call-stack is captured using the backtrace() call from glibc.…”

Section: Tracementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Automating the Application Data Placement in Hybrid Memory Systems

Servat

Peña

Llort

et al. 2017

2017 IEEE International Conference on Cluster Computing (CLUSTER)

View full text Add to dashboard Cite

show abstract

“…SLO uses a modified GCC compiler [23] to instrument every memory access instruction to collect data reuse information. Another compiler-based tool is MACPO [24]. MACPO uses profile feedback from UT's PerfExpert [25] tool to instrument memory accesses in problematic code regions using the LLVM compiler infrastructure [26].…”

Section: Related Workmentioning

confidence: 99%

Pinpointing data locality bottlenecks with low overhead

Liu

Mellor-Crummey

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

View full text Add to dashboard Cite

A wide gap exists between the speed of modern processors and memory subsystems. As a result, long latencies associated with fetching data from memory often significantly degrade execution performance. To aid with program tuning, application developers need tools to analyze memory access patterns and guide them how to reuse data in the fastest levels of a system's memory hierarchy. In this paper, we describe a novel, efficient, and effective tool for data locality measurement and analysis. Unlike other tools, our tool uses both statistical PMU sampling to quantify the cost of data locality bottlenecks and cache simulation to compute reuse distance to diagnose the causes of locality problems. This approach enables us to collect rich information to provide insight into a program's data locality problems. Our tool attributes quantitative measurements of observed memory latency to program variables and dynamically allocated data, as well as code. Our tool identifies data touched by reuse pairs and the accesses involved, identified with their full calling context. Finally, our tool employs both sampling and parallelization to accelerate the computation of representative reuse distance information. Experiments show that with an overhead of only about 13%, our tool provides detailed insights that enabled us to make non-trivial improvements to memorybound HPC benchmarks.

show abstract

“…Simulation-based data-centric tools, such as CPROF [23], MemSpy [27], ThreadSpotter [33], SLO [6,5], and MACPO [32], instrument some or all memory accesses and compute the approximate memory hierarchy response with a cache simulator. There are two drawbacks to simulation.…”

Section: Introductionmentioning

confidence: 99%

A data-centric profiler for parallel programs

Liu

Mellor-Crummey

2013

Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis

View full text Add to dashboard Cite

It is difficult to manually identify opportunities for enhancing data locality. To address this problem, we extended the HPCToolkit performance tools to support data-centric profiling of scalable parallel programs. Our tool uses hardware counters to directly measure memory access latency and attributes latency metrics to both variables and instructions. Different hardware counters provide insight into different aspects of data locality (or lack thereof). Unlike prior tools for data-centric analysis, our tool employs scalable measurement, analysis, and presentation methods that enable it to analyze the memory access behavior of scalable parallel programs with low runtime and space overhead. We demonstrate the utility of HPCToolkit's new data-centric analysis capabilities with case studies of five well-known benchmarks. In each benchmark, we identify performance bottlenecks caused by poor data locality and demonstrate non-trivial performance optimizations enabled by this guidance.

show abstract

Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics

Cited by 30 publications

References 11 publications

Automating the Application Data Placement in Hybrid Memory Systems

Automating the Application Data Placement in Hybrid Memory Systems

Pinpointing data locality bottlenecks with low overhead

A data-centric profiler for parallel programs

Contact Info

Product

Resources

About