Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability

Abstract

Current-oriented operational amplifier (OpAmp) design has been common for its orderly current-to-speed tradeoff. However, for high-precision or high-linearity applications, increasing the current does not help much, as the supply voltage (V DD ) and intrinsic gain of the MOSFETs in ultra-scaled CMOS technologies are very limited. This paper introduces voltage-oriented circuit techniques to address such limitations. Specifically, a 2xV DD -enabled recycling folded cascade (RFC) OpAmp is proposed. It features: (1) current recycling to enhance the effective trans conductance by 4x with no extra power; (2) transistor stacking to boost the output resistance by one to two orders of magnitude; and (3) V DD elevating to enlarge the linear output swing by 4x. Comparing with its 1xV DD RFC and FC counterparts, the proposed solution achieves 20-dB higher DC gain (i.e. 72.8 dB) in open loop and 20-dB lower IM3 (i.e., -76.5 dB) in closed loop, under the same power budget of 0.6 mW in a 1-V General Purpose 65-nm CMOS process. In many applications, these joint improvements in a single stage are already adequate, being more power efficient (i.e. less current paths), stable (i.e. more phase margin), and compact (i.e. no frequency compensation) than multi-stage OpAmps. Voltage-conscious biasing and node-voltage trajectory check ensure the device reliability in both transient and steady states. No specialized high-voltage device is necessary.

Reliability‐aware design of temporal neuromorphic encoder for image recognition

“…Several brain‐inspired circuits have been developed as a result of extensive research in the field of neuromorphic VLSI. The development of various circuits on a silicon chip at advanced CMOS technology nodes has elevated device reliability issues, which eventually degrades the circuit performance 22–26 . Device reliability issues like bias temperature instability (BTI) and hot carrier injection (HCI) are major concerns in integrated chips 27–29 .…”

“…The development of various circuits on a silicon chip at advanced CMOS technology nodes has elevated device reliability issues, which eventually degrades the circuit performance. [22][23][24][25][26] Device reliability issues like bias temperature instability (BTI) and hot carrier injection (HCI) are major concerns in integrated chips. [27][28][29] BTI and HCI lead to a shift in device parameters like the threshold voltage (V TH ), drain current (I D ), subthreshold slope (SS), transconductance (g m ).…”

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

“…This results in creation of higher electric field intensities in the gate oxide aggravating the BTI. The BTI effect, in turn, degrades the performance of integrated circuits .…”