Enrely: A reliable MLC PCM Architecture based on Data Encoding

Imran, Muhammad; Kwon, Taehyun; Yang, Joon-Sung

doi:10.1109/itc-cscc.2019.8793420

Cited by 2 publications

(4 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…W. -S. Khwa et al proposed a resistance drift compensation scheme for MLC PCM to mitigate against R-drift without such compromises [ 12 ]. M. Imran et al put forward an MLC PCM architecture based on effective data encoding with a simple flip operation applied to the data prior to a write to enhance the reliability of MLC PCM [ 13 ]. Different encoding techniques have also been proposed which can considerably enhance the reliability.…”

Section: Introductionmentioning

confidence: 99%

Enhancing the Data Reliability of Multilevel Storage in Phase Change Memory with 2T2R Cell Structure

Wang

Chen

et al. 2021

Micromachines

View full text Add to dashboard Cite

Multilevel storage and the continuing scaling down of technology have significantly improved the storage density of phase change memory, but have also brought about a challenge, in that data reliability can degrade due to the resistance drift. To ensure data reliability, many read and write operation technologies have been proposed. However, they only mitigate the influence on data through read and write operations after resistance drift occurs. In this paper, we consider the working principle of multilevel storage for PCM and present a novel 2T2R structure circuit to increase the storage density and reduce the influence of resistance drift fundamentally. To realize 3-bit per cell storage, a wide range of resistances were selected as different states of phase change memory. Then, we proposed a 4:3 compressing encoding scheme to transform the output data into binary data states. Therefore, the designed 2T2R was proven to have optimized storage density and data reliability by monitoring the conductance distribution at four time points (1 ms, 1 s, 6 h, 12 h) in 4000 devices. Simulation results showed that the resistance drift of our proposed 2T2R structure can significantly improve the storage density of multilevel storage and increase the data reliability of phase change memory.

show abstract

Section: Introductionmentioning

confidence: 99%

Enhancing the Data Reliability of Multilevel Storage in Phase Change Memory with 2T2R Cell Structure

Wang

Chen

et al. 2021

Micromachines

View full text Add to dashboard Cite

show abstract

“…Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.Electronics 2020, 9, 626 2 of 16 MLC PCM as the main memory or a storage class memory (SCM). Indeed, various methods have been introduced to use the MLC technology effectively when targeting PCM as the main memory [7][8][9][10][11][12][13][14][15].For reliable data retention, and for coping with the reduced sensing margin, iterative write-and-verify (read) operations must be executed for each memory cell in the MLC PCM, which deteriorates its lifetime and performance. In addition, MLC PCM suffers from a significantly higher soft error rate (SER) when compared to DRAM.…”

mentioning

confidence: 99%

“…Thus, recent studies have attempted to deploy 3LC PCM as a promising alternative to DRAM as the main memory. The motivations of this trial are based on the observation that 3LC PCM can show an improved storage density compared to 4LC PCM with ECC in the same SER environment [7,9,14,[18][19][20][21]. However, the existing 3LC PCM based architectures have a problem that the storage density does not approach the theoretical maximum of 160% due to an additional data conversion from binary to ternary.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

et al. 2020

View full text Add to dashboard Cite

Multi-level cell (MLC) phase-change memory (PCM) is an attractive solution for next-generation memory that is composed of resistance-based nonvolatile devices. MLC PCM is superior to dynamic random-access memory (DRAM) with regard to scalability and leakage power. Therefore, various studies have focused on the feasibility of MLC PCM-based main memory. The key challenges in replacing DRAM with MLC PCM are low reliability, limited lifetime, and long write latency, which are predominantly affected by the most error-vulnerable data pattern. Based on the physical characteristics of the PCM, where the reliability depends on the data pattern, a tri-level-cell (3LC) PCM has significantly higher performance and lifetime than a four-level-cell (4LC) PCM. However, a storage density is limited by binary-to-ternary data mapping. This paper introduces error-vulnerable pattern-aware binary-to-ternary data mapping utilizing 3LC PCM without an error-correction code (ECC) to enhance the storage density. To mitigate the storage density loss caused by the 3LC PCM, a two-way encoding is applied. The performance degradation is minimized through parallel encoding. The experimental results demonstrate that the proposed method improves the storage density by 17.9%. Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.Electronics 2020, 9, 626 2 of 16 MLC PCM as the main memory or a storage class memory (SCM). Indeed, various methods have been introduced to use the MLC technology effectively when targeting PCM as the main memory [7][8][9][10][11][12][13][14][15].For reliable data retention, and for coping with the reduced sensing margin, iterative write-and-verify (read) operations must be executed for each memory cell in the MLC PCM, which deteriorates its lifetime and performance. In addition, MLC PCM suffers from a significantly higher soft error rate (SER) when compared to DRAM. This is mainly caused by the resistance drift phenomenon that blurs the sensing boundary between adjacent states. The use of error-correction code (ECC) is a common technique in reducing the SER of MLC PCM; however, it adversely affects the performance and area efficiency.Scrubbing can help diminish the SER by reading, detecting, and correcting errors by utilizing the parity bit check and writing them back into the cell [16]. The shorter the scrubbing period, the lower the SER. However, frequent scrubbing accelerates the wearing out of PCM. In [10], the authors proposed an efficient scrubbing mechanism that could flexibly determine the scrubbing period considering the error-vulnerable patterns. In addition, recent studies focused on designing reliable 4LC PCM to mitigate the overhead caused by ECC and scrubbing, by expelling the most error-vulnerable pattern [7][8][9][10][11][12].Obviously, long ECC decoding latency is a significant bottleneck in achieving a high-performance memory system [17]. Moreover, complicated ECC algorithms are unacceptable in the MLC PCM based main memory ...

show abstract

Enrely: A reliable MLC PCM Architecture based on Data Encoding

Cited by 2 publications

References 6 publications

Enhancing the Data Reliability of Multilevel Storage in Phase Change Memory with 2T2R Cell Structure

Enhancing the Data Reliability of Multilevel Storage in Phase Change Memory with 2T2R Cell Structure

Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

Contact Info

Product

Resources

About