Ensemble Learning strategy in modeling of future generation nanoscale devices using Machine Learning

Ghoshhajra, Rachita; Biswas, Kalyan; Sultana, Mahamuda; Sarkar, Angsuman

doi:10.1109/devic57758.2023.10134917

Cited by 3 publications

(1 citation statement)

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“…VER the past few years a number of fields have benefited from developments in machine learning (ML) beyond computer science [1], [2]. In recent times, ML techniques have emerged as valuable tools for enhancing semiconductor device modeling for electronic design automation [3][4][5][6]. Previous studies have demonstrated that ML has the capacity to effectively address a variety of semiconductor challenges [7][8][9][10][11], particularly in the context of device modeling tasks [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

Butola,

Li,

Kola

2023

IEEE Open J. Nanotechnol.

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Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domain. One major advantage of ML-based compact modeling is its ability to capture complex relationships and patterns in large datasets. Therefore, in this paper a novel design scheme based on dynamically adaptive neural network (DANN) is proposed to develop fast and accurate compact model (CM). This framework constitutes a powerful yet computationally efficient methodology and exhibits emergent dynamic behaviors. This paper demonstrates that the compact model based on ML can be designed to replicate the performance of conventional compact model for nanodevices. For this work, gate-all-around (GAA) nanosheet (NS) device characteristics are comprehensively analyzed for process variability sources using the proposed model. The device geometry parameters such as channel length, nanosheet width and nanosheet thickness are fed as input features to the DANN model. The adaptive neural network learns dynamically by updating weights of the model in accordance with the input features and achieves accurate neural weight convergence. The proposed model predicted the electrical characteristics of NS devices with less than 1% error rate. The model is also implemented and validated for the simulations of digital circuit designs such as inverter, and logic gates.

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