Environmental-Based Characterization of SoC-Based Instrumentation Systems for Stratified Testing

Park, N.-J.; George, K. E.; Park, N.; Choi, Minsu; Kim, Yong-Bin; Lombardi, Fabrizio

doi:10.1109/tim.2005.847131

Cited by 2 publications

(1 citation statement)

References 29 publications

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“…To meet the challenges of future technologies for circuits we need a robust approach for the realization of defect level with high confidence of a circuit [1,2,3,4,5,6,7]. The needs of emerging technologies are centered around defect tolerance, both in the manufacturing stage and during operation.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Evaluation of Threshold Defect Tolerance

Patitz

Park

2008

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

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This paper presents a theoretical study on the threshold defect tolerance level. A new defect level model is proposed and used as a basis for the study in order to facilitate a theoretical modeling and evaluation of defect tolerance under a circumstance in which conventional testing processes are not practically viable. A comprehensive and thorough defect classification and characterization is conducted under specific design constraint when traditional testing is not practically deployable. An approach to an extensive theoretical and parametric compilation and optimization will be introduced in order to reveal a theoretical threshold defect tolerance level at which each choice defect tolerance method and strategy can be justified. The simulation results reveal there exists a theoretical threshold of defect tolerance level that will help guide the test and defect tolerance engineers to identify the optimal and viable testing and defect tolerance level.

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