An innovative solder bumping technology, termed squeegee bumping, has been developed at Motorola's Interconnect Systems Laboratory that uses baked photoresist as a inask for solder printing to deposit fine pitch solder humps o n , wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to stencil printing and therefore exhibits better versatility of solder materials selection than the electroplating process.Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show au average bump height of 118*3.5im, and a maximum-tominimum bump height range of 17pm over a 150mni-diameter wafer have been produced repeatedly on test wafers with 2 1 0 p peripheral pitch. A 109.6*1.3pm bump height on orthogonal array with 250i1n pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal I humidity storage procedures.No degradation of shear strength was observed after up to 10X reflows and 1,008 hours of a thermal I humidity strcss environment. Bump reliability was also cvaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55°C to +12S0C had a characteristic life oC 2,764 cycles with a 1" failure at 1,050 cycles. No failures were observed after 432 hours of autoclave stress at 12I0C, 100%RH, 15 psig test condition.