Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Durfee, Curtis; Otto IV, Ivo; Kal, Subhadeep; Pancharatnam, Shanti; Flaugh, Matthew; Kanaki, Toshiki; Rednor, Matthew; Zhou, Huimei; Qin, Liqiao; Meli, Luciana; Loubet, Nicolas; Biolsi, Peter; Felix, Nelson

doi:10.1149/11201.0045ecst

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…1. In the near term, triple-gate fin field-effect-transistors (finFETs) are being replaced by gateall-around (GAA) nanosheet (NS) FETs consisting of several vertically stacked lateral NS per device (21)(22)(23)(24)(25)(26)(27)(28)(29). The latter offer better electrostatics control and short-channel immunity allowing further gate length (Lgate) scaling.…”

Section: Nanosheet-based Fet Transistorsmentioning

confidence: 99%

(Invited) Advanced Compute Scaling: A New Era of Exciting, Sustainability-Aware Innovations with Nanosheet-Based Devices, Increased Interdisciplinary Synergies, and (R)Evolution Towards Higher Versatility

Veloso,

Eneman,

Vermeersch

et al. 2024

ECS Trans.

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We report on several key elements for enabling advanced compute scaling. At transistor level, as we are entering the nanosheet (NS) era, the focus lies on single-level NSFETs consisting of several vertically stacked NS per device, which can evolve into 3D stacked configurations like the so-called complementary FET (CFET) with potentially different materials/crystal orientations for the stacked channels. New device connectivity schemes are also becoming possible thanks to the trend towards using both wafer sides, started with the move of on-chip power distribution to the wafer’s backside. As devices are becoming sandwiched and accessed from levels above and below them, that also allows interesting new opportunities for transistor engineering, some examples of which will be discussed here. In parallel, from a system level’s perspective, a (r)evolution towards smart disintegration, enabling higher flexibility and hybridized technology platforms, is expected to further allow new scaling paths, also as it can help ease the introduction of new materials and device architectures.

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Section: Nanosheet-based Fet Transistorsmentioning

confidence: 99%

(Invited) Advanced Compute Scaling: A New Era of Exciting, Sustainability-Aware Innovations with Nanosheet-Based Devices, Increased Interdisciplinary Synergies, and (R)Evolution Towards Higher Versatility

Veloso,

Eneman,

Vermeersch

et al. 2024

ECS Trans.

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“…The inner spacer structure aims to mitigate parasitic capacitance (C gg ) between the gate and the Source/Drain of SiGe/Si stacked GAA-NSTs, 7,8 and controlls Source/Drain extension during the channel release process after dummy gate removal. 9 The inner spacer module is one of the critical modules in the fabrication process of GAA nanosheet (NS) devices and presents significant challenges. 10 As shown in Fig.…”

mentioning

confidence: 99%

Study of Inner Spacer Module Process for Gate All Around Field Effect Transistors

Yang,

Li,

Liu

et al. 2024

ECS J. Solid State Sci. Technol.

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Gate-All-Around(GAA) transistor is the most competitive device for the replacement of Fin Field-Effect Transistor (FinFET). Integrating the inner spacer module into process flow of manufacturing GAA devices still faces significant challenges.In this study, dummy gates were included and the most critical processes for inner spacer, such as cavity etching, dielectric material conformal filling and precise etching back process were studied.The inner spacer cavity with a depth of 10.10 nm was achieved using isotropic etching, and dielectric filling was completed by low pressure chemical deposition (LPCVD).Finally, an inner spacer with 9.35 nm thickness is formed after precise etching the dielectric material. Furthermore，to verify the physical isolation of the inner spacer, a selective epitaxy was developed on the Source/Drain region, achieving better process results. This research will provide important references for the industry to manufacture GAA devices, especially inner spacers.

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Development of Epitaxial SiGeB as a Test Vehicle to Evaluate Source-Drain Etchout During Channel Release of Gate-all-Around Devices: Topic/category: AEPM: Advanced Equipment Processes and Materials

Nasseri,

Durfee,

et al. 2024

2024 35th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

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Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Cited by 3 publications

References 9 publications

(Invited) Advanced Compute Scaling: A New Era of Exciting, Sustainability-Aware Innovations with Nanosheet-Based Devices, Increased Interdisciplinary Synergies, and (R)Evolution Towards Higher Versatility

(Invited) Advanced Compute Scaling: A New Era of Exciting, Sustainability-Aware Innovations with Nanosheet-Based Devices, Increased Interdisciplinary Synergies, and (R)Evolution Towards Higher Versatility

Study of Inner Spacer Module Process for Gate All Around Field Effect Transistors

Development of Epitaxial SiGeB as a Test Vehicle to Evaluate Source-Drain Etchout During Channel Release of Gate-all-Around Devices: Topic/category: AEPM: Advanced Equipment Processes and Materials

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