EPIC: Explicitly Parallel Instruction Computing

Schlansker, Michael; Rau, B. Ramakrishna

doi:10.1109/2.820037

Cited by 106 publications

(48 citation statements)

References 4 publications

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“…Using this, compiler performs instruction scheduling and optimization, and then sends the information of optimization to hardware to guide the pipeline execution. Furthermore, EPIC emphasizes adaptive adjustment according to the dynamic changes of hardware resources [3]. This paper proposes a Reduced Explicitly Parallel Instruction Computing Processor (REPICP) which is a 64-bit general-purpose microprocessor.…”

Section: Introductionmentioning

confidence: 99%

Architecture and Implementation of a Reduced EPIC Processor

Gao¹,

Zhang²,

Zhang³

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper proposes a Reduced Explicitly Parallel Instruction Computing Processor (REPICP) which is an independently designed, 64-bit, general-purpose microprocessor. The REPICP based on EPIC architecture overcomes the disadvantages of hardware-based superscalar and software-based Very Long Instruction Word (VLIW) and utilizes the cooperation of compiler and hardware to enhance Instruction-Level Parallelism (ILP). In REPICP, we propose the Optimized Lock-Step execution Model (OLSM) and instruction control pipeline method. We also propose reduced innovative methods to optimize the design. The REPICP is fabricated in Artisan 0.13 µm Nominal 1P8M process with 57 M transistors. The die size of the REPICP is 100 mm 2 (10 × 10), and consumes only 12 W power when running at 300 MHz.

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Section: Introductionmentioning

confidence: 99%

Architecture and Implementation of a Reduced EPIC Processor

Gao¹,

Zhang²,

Zhang³

et al. 2013

IEICE Trans. Inf. & Syst.

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“…3a), accessible from all the Contexts/HCs in that system, and a configurable, instruction RAM (IRAM). Both memories are parametric and multi-banked.VThreads relies on an ISA-agnostic pipelined micro-architecture with partial support for fully-predicated (EPIC) [19] and full support for partially-predicated (Multiflow-type) statically-scheduled, long instruction word architectures [20]. These are known as perspectives with the default perspective (VT32PP) being the 32-bit partially-predicated VLIW architecture.…”

Section: Vthreads Overviewmentioning

confidence: 99%

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

Chouliaras

Stevens

Dwyer

2016

Microprocessors and Microsystems

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performance increase on synthetic benchmarks, x5 on a parallel Mandelbrot implementation, 66% better on a threaded JPEG implementation, 79% better on an edge-detection benchmark and~13% improvement on DES compared to the Leon3MP CMP. In the range of 2 to 8 cores VThreads demonstrates a post-route (statistical) power reduction between 65% to 57% at an area increase of 1.2%-10% for 1-8 cores, compared to a similarly-configured Leon3MP CMP. This combination of micro-architectural features, scalability, extensibility, hardware support for low-latency PThreads, power efficiency and area make the processor an attractive proposition for low-power, deeply-embedded applications requiring minimum OS support.

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“…Rather than relying on hardware to figure out which instructions could be executed in parallel, VLIW architectures specify this information explicitly. Explicitly Parallel Instruction Computing (EPIC) [26] architectures were developed as an extension to VLIW that gave the compiler even more control over execution. Transport Triggered Architectures (TTAs) [6] are similar to VLIW architectures, except that they allow values to be explicitly passed between the ports of functional units.…”

Section: Instruction Set Architecturesmentioning

confidence: 99%