Epitaxially-grown GaN junction field effect transistors

Abstract

ABSTRACTcalculated from the measured g , and the source series resistance, is 81 mS/mm. The fT and fmax for these devices are 6 GHz and 12 GHz, respectively. These JFETs exhibit a significant current reduction after a high drain bias is applied, which is attributed to a partially depleted channel caused by trapped hot-electrons in the semi-insulating GaN buffer layer. A theoretical model describing 1 the current collapse is described, and an estimate for the length of the trapped electron region is given.

Trapping effects in GaN and SiC microwave FETs

“…Zhang et al [41] suggested that the significant reduction in dc drain current that they observed in GaN junction FETs (FETs) after application of high drain bias was a result of high field injection and subsequent trapping of electrons in the HR GaN buffer layer. Kuliev et al [42] observed a significant collapse in the dc drain current of a GaN MESFET subjected to reverse gate diode bias stress and UV illumination was found to recover the current collapse.…”

A Physics-Based Frequency Dispersion Model of GaN MESFETs

“…GaN-based devices are plagued with traps that lead to current collapse in the cureent-voltage (/-V) characteristics [6]- [9], which results in severe performance degradation at high-power and high-fi^equency applications. Zhang et al [6] high drain bias and proposed an estimation of the length of the trapped charge region along the channel, at the channel-substrate interface.…”

“…Zhang et al [6] high drain bias and proposed an estimation of the length of the trapped charge region along the channel, at the channel-substrate interface. Klein et al [7] have reported current collapse in GaN MESFETs in the absence of light.…”

“…+ -^eW (6) where VBG is the drain-to-gate voltage. The second term in (5) and (6) represents the contributions from drain and source sidewalls [16].…”

NONLINEAR MODELING OF TRAPPING AND THERMAL EFFECTS ON GaAs AND GaN MESFET/HEMT DEVICES

“…2 shows the pulsed I-V characteristics of the same device under these conditions. While the effects of gate-lag are normally attributed to surface traps, the effects of drain-lag are mainly due to traps present in the buffer and the substrate region [29,30]. The problems that arise from gate-lag can be reduced by improved passivation.…”