Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections

Hur, Y.; Maeng, M.; Chun, C.; Bien, Franklin; Kim, Hyoungsoo; Chandramouli, S.; Gebara, E.; Laskar, J.

doi:10.1109/tmtt.2004.839311

Cited by 42 publications

(19 citation statements)

References 9 publications

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“…The vertical opening of the histogram is 1 mV and we record 5000 data points in the histogram. The rms jitter is recorded from the histogram and we use (10) to calculate the forward coupling time constant and compare it with the results in Fig. 5.…”

Section: A 2-pammentioning

confidence: 99%

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Cancellation of Crosstalk-Induced Jitter

Buckwalter

Hajimiri

2006

IEEE J. Solid-State Circuits

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Abstract-A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-speed serial links. A simple model of electromagnetic coupling demonstrates the generation of crosstalk-induced jitter. The analysis highlights unique aspects of crosstalk-induced jitter that differ from far-end crosstalk. The model is used to predict the crosstalk-induced jitter in 2-PAM and 4-PAM, which is compared to measurement. Furthermore, the model suggests an equalizer that compensates for the data-induced electromagnetic coupling between adjacent links and is suitable for pre-or post-emphasis schemes. The circuits are implemented using 130-nm MOSFETs and operate at 5-10 Gb/s. The results demonstrate reduced deterministic jitter and lower bit-error rate (BER). At 10 Gb/s, the crosstalk-induced jitter equalizer opens the eye at 10 12 BER from 17 to 45 ps and lowers the rms jitter from 8.7 to 6.3 ps.

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Section: A 2-pammentioning

confidence: 99%

“…For instance, wiring capacitances tend to dominate interconnect crosstalk on-chip and backplane connectors introduce multi-pin crosstalk. Recent work has addressed crosstalk amplitude equalization issues between neighboring serial links [8]- [10]. Crosstalk considerations also affect the performance of integrated digital circuits [11].…”

mentioning

confidence: 99%

Cancellation of Crosstalk-Induced Jitter

Buckwalter

Hajimiri

2006

IEEE J. Solid-State Circuits

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“…For example, electrical-domain compensation using multipurpose digital-signal processors (DSPs) has been reported; in this approach digital filters, such as finite impulse response (FIR) filters, are calculated by the DSPs [2,3]. On the other hand, analog FIR filters based on analog electronic circuit technology are also attractive for achieving cost-effectiveness and low power consumption [4,5,6,7,8]. We have investigated analog FIR filters using binary delay-line components based on complementary metal-oxide-semiconductor (CMOS) inverters which can realize smaller integrated-circuit (IC) chip size [9].…”

Section: Introductionmentioning

confidence: 99%

Multilevel pre-equalization using an analog FIR filter with multiple binary delay lines for 20-Gb/s 4-PAM multimode fiber transmission

Nakamura

Amino

Sekine

et al. 2018

IEICE Electron. Express

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We propose a novel multilevel pre-equalizer using an analog FIR filter having multiple binary delay lines composed of CMOS inverters. The proposed pre-equalizer can decrease the required circuit scale of conventional analog FIR filters based on binary delay lines. The required number of multiplier circuits was halved by the proposed design scheme in the case of four-level pulse amplitude modulation (4-PAM). The performance was investigated using numerical simulation of a 20-Gb/s 4-PAM multimode fiber (MMF) transmission system. The proposed pre-equalizer successfully compensated the 4-PAM signals, improving the error vector magnitude (EVM) from 40% to 21%.

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“…Electrical domain compensation using multipurpose digital-signal processors (DSPs) has also been studied; in this approach digital filters such as finite impulse response (FIR) filters are calculated by the DSPs [3,4]. On the other hand, analog FIR filters based on analog electronic circuit technology are also attractive for realizing cost-effectiveness and low power consumption [5,6,7,8]. We have investigated analog FIR filters using binary delay-line components based on complementary metal-oxide-semiconductor (CMOS) inverters, which can realize smaller integrated-circuit (IC) chip-size [9].…”

Section: Introductionmentioning

confidence: 99%

Multi-level pre-equalization using binary analog FIR filters based on 28-nm FD-SOI for 20-Gb/s 4-PAM multi-mode fiber transmission

et al. 2017

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Abstract:We propose a novel multi-level pre-equalizer composed of multiple binary analog finite impulse response (FIR) filters. The performance was investigated using numerical simulation of a 20-Gb/s four-level pulseamplitude-modulation (4-PAM) multi-mode fiber (MMF) transmission system. The analog FIR filters were designed using 28 nm fully depleted silicon on insulator (FD-SOI) based complementary metal-oxide-semiconductor (CMOS) circuits. The simulated CMOS circuits successfully compensated the multi-level signals distorted by modal dispersion. The error vector magnitude (EVM) of the transmitted 4-PAM signals was improved from 40% to 9%. The proposed design scheme will enable cost-effective, lowpower analog FIR filters for multi-level pre-equalization. Keywords: equalization, pre-distortion, FIR filter, 4-PAM, multi-mode fiber, CMOS circuit Classification: Fiber-Optic Transmission for CommunicationsNyquist pulse-amplitude modulation (PAM) signaling for 100-Gbit/s/λ optical short-reach transmission," European Conference on Optical Communication (ECOC2014), P.

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Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections

Cited by 42 publications

References 9 publications

Cancellation of Crosstalk-Induced Jitter

Cancellation of Crosstalk-Induced Jitter

Multilevel pre-equalization using an analog FIR filter with multiple binary delay lines for 20-Gb/s 4-PAM multimode fiber transmission

Multi-level pre-equalization using binary analog FIR filters based on 28-nm FD-SOI for 20-Gb/s 4-PAM multi-mode fiber transmission

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