Equivalence Checking of Static Affine Programs Using Widening to Handle Recurrences

Verdoolaege, Sven; Janssens, Gerda; Bruynooghe, Maurice

doi:10.1007/978-3-642-02658-4_44

Cited by 41 publications

(62 citation statements)

References 13 publications

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“…Verdoolaege et al [45] propose an algorithm to prove the equivalence of integer affine programs where loops are described as recurrences. The algorithm does not compute the closed-form solution for the recurrences, but instead uses widening to reach a fixed point.…”

Section: Related Workmentioning

confidence: 99%

Automatic Equivalence Checking of UF+IA Programs

Lopes

Monteiro

2013

Model Checking Software

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Abstract. Proving the equivalence of programs has several important applications, including algorithm recognition, regression checking, compiler optimization verification, and information flow checking. Despite being a topic with so many important applications, program equivalence checking has seen little advances over the past decades due to its inherent (high) complexity. In this paper, we propose, to the best of our knowledge, the first algorithm for the automatic verification of partial equivalence of two programs over the combined theory of uninterpreted function symbols and integer arithmetic (UF+IA). The proposed algorithm supports, in particular, programs with nested loops. The crux of the technique is a transformation of uninterpreted functions (UFs) applications into integer polynomials, which enables the summarization of loops with UF applications using recurrences. The equivalence checking algorithm then proceeds on loop-free, integer only programs. We implemented the proposed technique in CORK, a tool that automatically verifies the correctness of compiler optimizations, and we show that it can prove more optimizations correct than state-of-the-art techniques.

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Section: Related Workmentioning

confidence: 99%

Automatic Equivalence Checking of UF+IA Programs

Lopes

Monteiro

2013

Model Checking Software

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“…In earlier work [11], we presented an automated approach to regression verification based on invariant generation using Horn clauses. Many other approaches [2,16,31,32,39] exist to regression verification for imperative programming languages.…”

Section: Related Workmentioning

confidence: 99%

Regression Verification for Programmable Logic Controller Software

Beckert

Ulbrich

Vogel‐Heuser

et al. 2015

Formal Methods and Software Engineering

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Abstract. Automated production systems are usually driven by Programmable Logic Controllers (PLCs). These systems are long-living -yet have to adapt to changing requirements over time. This paper presents a novel method for regression verification of PLC code, which allows one to prove that a new revision of the plant's software does not break existing intended behavior. Our main contribution is the design, implementation, and evaluation of a regression verification method for PLC code. We also clarify and define the notion of program equivalence for reactive PLC code. Core elements of our method are a translation of PLC code into the SMV input language for model checkers, the adaptation of the coupling invariants concept to reactive systems, and the implementation of a toolchain using a model checker supporting invariant generation. We have successfully evaluated our approach using the Pick-and-Place Unit benchmark case study.

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“…First, equivalence checking/testing [22], [23] can be used to check if a hardware (resp. software) product complies with the hardware (resp.…”

Section: A Applicationsmentioning

confidence: 99%

Formalizing hardware/software interface specifications

Xie

Ball

et al. 2011

2011 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011)

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Abstract-Software drivers are usually developed after hardware devices become available. This dependency can induce a long product cycle. Although co-simulation and co-verification techniques have been utilized to facilitate the driver development, Hardware/Software (HW/SW) interface models, as the test harnesses, are often challenging to specify. Such interface models should have formal semantics, be efficient for testing, and cover all HW/SW behaviors described by HW/SW interface protocols. We present an approach to formalizing HW/SW interface specifications, where we propose a semantic model, relative atomicity, to capture the concurrency model in HW/SW interfaces; demonstrate our approach via a realistic example; elaborate on how we have utilized this approach in device/driver development process; and discuss criteria for evaluating our formal specifications. We have detected fifteen issues in four English specifications. Furthermore, our formal specifications are readily useful as the test harnesses for co-verification, which has discovered twelve real bugs in five industrial driver programs.

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Equivalence Checking of Static Affine Programs Using Widening to Handle Recurrences

Cited by 41 publications

References 13 publications

Automatic Equivalence Checking of UF+IA Programs

Automatic Equivalence Checking of UF+IA Programs

Regression Verification for Programmable Logic Controller Software

Formalizing hardware/software interface specifications

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