Equivalent inductance of power‐distribution planes in multilayer printed circuit boards and capacitor allocation for decoupling

Abstract

SUMMARYIn order to obtain a design guideline related to the optimum allocation of decoupling capacitor to reduce unwanted electromagnetic wave radiation due to voltage variation and to supply the charge needed for chip operation in a multilayered printed circuit board, the equivalent inductance of the power distribution system is quantitatively analyzed. The power distribution system is represented by a two-dimensional equivalent circuit network and is analyzed. It is found that the parasitic inductance becomes smaller as the distance between the power distribution plane and the ground plane decreases. Further, this result is applied to optimum allocation of the capacitor near the LSI power distribution pin for suppression of LSI malfunctions and to quantification of the radiation suppression effect of capacitor allocation near the via hole that is generated in the interconnect processing of the signal pattern through the power distribution plane and the ground plane. The relationship of the spacing between the planes to the distance between the power distribution pin and the capacitor is formulated so as to keep the power distribution voltage variations within a certain range. Also formulated is the relationship of the radiation suppression effect to the distance between the via hole and the capacitor location in order to obtain constant radiation suppression efficiency. In this way, specific design values of capacitor allocation are obtained for suppression of LSI malfunctions and unwanted electromagnetic radiation.