Equivalent victim model of the coupled interconnects for simulating crosstalk induced glitches and delays

Hasan, Shehzad; Palit, A.K.; Anheier, W.

doi:10.1109/spi.2009.5089850

Cited by 6 publications

(4 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Due to the unceasing increase of the electronic system integration, the modern high-speed electronic equipment meets different technological roadblocks due to the interconnect complexity [10][11][12][13][14][15]. In addition to the investigation on the apparition of electromagnetic interferences (EMI) and electromagnetic compatibility (EMC), many works stating the power loss and the interconnect delay effects for example, in the RF/digital devices were done [6,[16][17][18][19][20][21][22][23]. Because of the undesired interconnection perturbations, it has been evidenced that the interconnect delays of high speed digital IC dominate widely gate delays [5].…”

Section: Introductionmentioning

confidence: 99%

“…During the data stream transmission, these technological issues can be sources of signal distortions, asynchronous effects of the transmitted analog signals and erroneous symbols. So, intensive researches were performed on the modeling of the interconnect networks in order to predict the signal integrity (SI) [9,[11][12][13][14][15][17][18][19][20][21][22][23][24]. To minimize the cost and energy consumption and also for sharing data and clock signals through multipath circuits can be composed of ICs packaged in different levels this later is fundamental [25][26][27][28].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Ravelo¹

2012

PIER B

View full text Add to dashboard Cite

Abstract-An accurate and behavioral modeling method of symmetrical T-tree interconnect network is successfully investigated in this paper. The T-tree network topology understudy is consisted of elementary lumped L-cells formed by series impedance and parallel admittance. It is demonstrated how the input-output signal paths of this single input multiple output (SIMO) tree network can be reduced to single input single output (SISO) network composed of L-cells in cascade. The literal expressions of the currents, the input impedances and the voltage transfer function of the T-tree electrical interconnect via elementary transfer matrix products are determined. Thus, the exact expression of the multi-level behavioral T-tree transfer function is established. The routine algorithm developed was implemented in Matlab programs. As application of the developed modeling method, the analysis of T-tree topology comprised of different and identical RLC-cells is conducted. To demonstrate the relevance of the model established, lumped RLC T-tree networks with different levels for the microelectronic interconnect application are designed and simulated. The work flow illustrating the guideline for the application of the routine algorithm summarizing the modeling method is proposed. Then, 3D-microstrip T-tree interconnects with width 0.1 µm and length 3 mm printed on FR4-substrate were considered. As results, a very good agreement between the results from the reduced behavioral model proposed and SPICE-computations is found both in frequency-and timedomains by considering arbitrary binary sequence "01001100" with 2 Gsym/s rate. The model proposed in this paper presents significant benefits in terms of flexibility and very less computation times. It can be used during the design process of the PCB and the microelectronic circuits for the signal integrity prediction. In the continuation of this 24Ravelo work, the modeling of clock T-tree interconnects for packaging systems composed of distributed elements using an analogue process is in progress.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Ravelo¹

2012

PIER B

View full text Add to dashboard Cite

show abstract

“…For the better understanding in the matter of the basic functioning of this technology, a large scientific background on the physical approach permitting an accurate analysis of the circuit and system equivalent behaviours or electrical modelling, electromagnetic (EM) effects on the wave propagation and also the mathematical approach for the signal theory are necessary [8][9][10][11][12][13]. The synergy of all these multiphysic fields constitutes the particularity of the signal integrity (SI) discipline which is one of major steps for investigating the analogue and digital high-speed systems.…”

Section: Introductionmentioning

confidence: 99%

“…Beyond the unintentional perturbation phenomena as the electromagnetic interference (EMI) and electromagnetic compatibility (EMC) emissions [8][9], this electronic printed circuit board (PCB) and IC design complexity can generate systematically a serious problematic in terms of SI and power integrity (PI) of the interconnection networks [10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Delay modeling of high-speed distributed interconnect for the signal integrity prediction

Raveloa

2012

Eur. Phys. J. Appl. Phys.

View full text Add to dashboard Cite

Abstract:A relevant modelling method of distributed interconnect line for the high-speed signal integrity (SI) application is introduced in this paper. By using the microwave and transmission line (TL) theory, the interconnect lines are assumed as its distributed RLC-model. Then, based-on the transfer matrix analysis, the second order global transfer function of the interconnect network comprised of the TL driven by voltage source including its internal resistance and the impedance load is expressed. Thus, mathematical analysis enabling the physical SI parameters extraction was established by using the transient response of the loaded line. To verify the relevance of the developed model, RC-and RLC-lines excited by square-wave-pulse with 10-Gbits/s-rate were investigated. So, comparisons with SPICE-computations were performed. As results, transient responses perfectly well-correlated to the reference SPICE-models were evidenced. As application of the introduced model, evaluations of rise-/fall-times, propagation delays, signal attenuations and even the settling times were realized for different values of TL parameters. Compared to other methods, the computation execution time and data-memory consumed by the program implementing the proposed delay modelling-method algorithm are much better.

show abstract

Modelling of the Signal Delay Induced by PCB Interconnect SISO Structure

Ravelo¹,

Eudes²

2019

Analytical Methodology of Tree Microstrip Interconnects Modelling for Signal Distribution

View full text Add to dashboard Cite

Equivalent victim model of the coupled interconnects for simulating crosstalk induced glitches and delays

Cited by 6 publications

References 6 publications

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

Delay modeling of high-speed distributed interconnect for the signal integrity prediction

Modelling of the Signal Delay Induced by PCB Interconnect SISO Structure

Contact Info

Product

Resources

About