Erratum to “Additional Nitrogen Ion-Implantation Treatment in STI to Relax the Intrinsic Compressive Stress for n-MOSFETs” [Aug 12 2033-2036]

Abstract

In our original work [1], we demonstrated the usage of N-IMP in STI SiO 2 to relax the compressive stress in the n-MOSFETs and further improve the core device performance accordingly.We wish to offer an apology for the typo in the original work and want to provide the new data/finding in the erratum paper. In this paper, we demonstrate the N-IMP stress effect on the Ge n-MOSFETs (the original article has a typo for Si). The TEM image on the Ge MOSFET is also shown for reference in Fig. 2r.Further investigation/application and the mechanism of this stress memory technology can also be found in [2]. Fig. 2r. (a) AFM-Raman signal in our standard sample. (b) AFM image.(c) TEM image on our Ge MOSFETs. The real size of the CD and STI regions in the real CMOS transistor is ∼300-400 nm. Based on the wave number of Ge-Ge phonon vibration in the Raman spectra, the intrinsic compressive stress in the Ge CD with the standard STI process is about 700 MPa. REFERENCES[1] M.Additional nitrogen ion-implantation treatment in STI to relax the intrinsic compressive stress for n-MOSFETs," IEEE Trans.

Enhancement of carrier mobility in metal-oxide semiconductor field-effect transistors using negative thermal expansion gate electrodes

“…Therefore, a large CTE mismatch can introduce a large strain into channel materials. 25,26) The CTE mismatch between the gate electrode and substrate also introduces strain into the channel material. TiN, which is usually used as the gate electrode, has a higher positive CTE than that of Si.…”