Error and flow control in terabit intelligent optical backplanes

Szymański, Tomasz; Tyan, Victor

doi:10.1109/2944.778318

Cited by 7 publications

(4 citation statements)

References 18 publications

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“…The clock period is determined by the largest delay and, therefore, the clock rate is (37) The power dissipated must be modified to include the power of the pipeline latches (DFFs) in the horizontal busses and the multiplexer trees, which is easily determined from (33). The power is given by (38) The latter two terms represent the input port and intrinsic capacitances of the DFF cell. The energy per bit switched (excluding the clock tree and memory) then becomes (39) The last term in the large bracket in (39) reflect the additional power consumed by the pipeline latches.…”

Section: A Broadcast Bussesmentioning

confidence: 99%

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Power complexity of multiplexer-based optoelectronic crossbar switches

Szymański

Gourgy

2005

IEEE Trans. VLSI Syst.

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The integration of thousands of optical input/output (I/O) devices and large electronic crossbar switching elements onto a single optoelectronic integrated circuit (IC) can place stringent power demands on the CMOS substrates. Currently, there is no sufficiently general analytic methodology for power analysis and power reduction of large-scale crossbar switching systems. An analysis of the power complexity of single-chip optoelectronic switches is presented, assuming the classic broadcast-and-select crossbar architecture. The analysis yields the distribution of power dissipation and allows for design optimization. Both unpipelined and pipelined designs are analyzed, and a technique to reduce power dissipation significantly is proposed. The design of a 5.12 Tbit single-chip optoelectronic switch using 0.18-m CMOS technology is illustrated. The pipelined switch design occupies 70 mm 2 of CMOS area, and consumes 80 W of power, which compares favorably to the power required in electrical crossbar switches of equivalent capacity.

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Section: A Broadcast Bussesmentioning

confidence: 99%

“…It has been argued that future multiTerabit systems will require much lower BERs, or strong error detecting/correcting codes [38]- [40] with high throughput and reasonable hardware complexity, to limit the effects of bit errors.…”

Section: Optical Power Budget and Bit Error Ratementioning

confidence: 99%

Power complexity of multiplexer-based optoelectronic crossbar switches

Szymański

Gourgy

2005

IEEE Trans. VLSI Syst.

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“…As part of the architectural innovation, the use of simple embedded FEC built directly onto a 2-D CMOS/VCSEL optical transceiver was proposed in [6]. The industrial sponsors, major Canadian manufacturers in the optical networking industry, were strongly opposed to the concept of embedding FEC directly onto CMOS/VCSEL transceivers, citing concerns about the hardware complexity of on-chip FECs, the loss of bandwidth due to the FEC overhead and the lack of tangible benefits to FEC.…”

Section: Introductionmentioning

confidence: 99%

“…The inner codes (encoded last and decoded first) consist of small linear block codes with reasonable FEC capability, such as small BCH or Hamming codes, or the Golay code, which can be encoded and decoded with reasonable hardware cost and delay. The outer codes for a complete packet consist of a long linear block code with excellent error detection (ED) ability, such as a cycle redundancy check (CRC) code or the multidimensional parity checks considered in [6] and [7]. Low-power pipelined on-chip encoders and decoders for the FEC and CRC codes are proposed.…”

Section: Introductionmentioning

confidence: 99%

Optical link optimization using embedded forward error correcting codes

Szymański

2003

IEEE J. Select. Topics Quantum Electron.

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Abstract-The design of a single-chip optical transceiver to optimize the performance of a short-distance optical datalink is proposed. The transceiver includes an embedded hybrid automatic repeat request (ARQ) controller capable of operation at several gigahertz clock rates. The hybrid ARQ controller uses a combination of packet retransmission protocols and forward error correction (FEC) to minimize bit errors and achieve a transmitter power coding gain of several dB. Conventional FEC codes such as Reed-Solomon codes cannot be used due to their excessive hardware cost and delays. A practical multilevel coding scheme is explored. The inner codes consist of small linear block codes with reasonable FEC capability, such as small BCH codes, which can be encoded and decoded with reasonable hardware cost and delay. The outer code for a complete packet consists of a long linear block code with excellent error detection ability, such as a cycle redundancy check code. Low-power pipelined on-chip FEC decoders with estimated throughputs of several hundred gigabits per second per square millimeter are proposed. Mathematical analysis indicates that substantial coding gains are possible, which can be used to increase the data rate or the distance span of the link. The proposed designs can be used in short-distance optical transceivers for 10-Gb ethernet, fiberchannel, and very short reach optical datalinks, and are scalable to future two-dimensional optical datalinks with Terabits of capacity.Index Terms-Automatic repeat request (ARQ), BCH, code, forward error correcting, optical link, pipelined, transceiver, very large scale integration.

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Impact of Future Trends on Exascale Grid and Cloud Computing

Szymański

2014

Lecture Notes in Computer Science

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Error and flow control in terabit intelligent optical backplanes

Cited by 7 publications

References 18 publications

Power complexity of multiplexer-based optoelectronic crossbar switches

Power complexity of multiplexer-based optoelectronic crossbar switches

Optical link optimization using embedded forward error correcting codes

Impact of Future Trends on Exascale Grid and Cloud Computing

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