Error-Backpropagation-Based Background Calibration of TI-ADC for Adaptively Equalized Digital Communication Receivers

Abstract

A novel background calibration technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs) is presented in this paper. This technique is applicable to equalized digital communication receivers. As shown in the literature, in a digital receiver it is possible to treat the TI-ADC errors as part of the communication channel and take advantage of the adaptive equalizer to compensate them. Therefore calibration becomes an integral part of channel equalization. No special purpose analog or digital calibration blocks or algorithms are required. However, there is a large class of receivers where the equalization technique cannot be directly applied because other signal processing blocks are located between the TI-ADC and the equalizer. The technique presented here generalizes earlier works to this class of receivers. The error backpropagation algorithm, traditionally used in machine learning, is applied to the error computed at the receiver slicer and used to adapt an auxiliary equalizer adjacent to the TI-ADC, called the Compensation Equalizer (CE). Simulations using a dual polarization optical coherent receiver model demonstrate accurate and robust mismatch compensation across different application scenarios. Several Quadrature Amplitude Modulation (QAM) schemes are tested in simulations and experimentally. Measurements on an emulation platform which includes an 8 bit, 4 GS/s TI-ADC prototype chip fabricated in 130nm CMOS technology, show an almost ideal mitigation of the impact of the mismatches on the receiver performance when 64-QAM and 256-QAM schemes are tested. INDEX TERMS Background calibration, error backpropagation, optical coherent receiver, TI-ADC, TI-ADC mismatch calibration. I. INTRODUCTION T HIS paper proposes a novel background calibration technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs) used in equalized digital communication receivers. It generalizes a previously proposed technique [1]-[3]. Current and emerging digital receivers for ultra highspeed communication systems [4]-[10] require large bandwidth, high sampling rate ADCs. Please see [11] and references therein for a recent review of interleaving techniques for high speed data converters. The TI-ADC has been the technique predominantly used to meet the demanding sampling rate and bandwidth requirements of high-speed transceivers [12], [13]. The per-formance of TI-ADCs is affected by mismatches among the interleaves [14], [15]. Mismatches of sampling time, gain, bandwidth, as well as DC offset, are the most common impairments. Many calibration techniques have been proposed in the literature. Please see [16]-[41] and references therein for a thorough review and discussion. Calibration techniques for general purpose TI-ADCs in general require dedicated calibration blocks and algorithms. On the other hand, several authors [1]-[3] have shown that in the special case of an equalized digital receiver, it is possible to treat the TI-ADC errors as integral part of the communication channel and take advantage of the already ex...

Digital Background Compensation of Analog Impairments in Jointly Frequency-Time Interleaved DACs

“…However, when the PTVE is implemented with a parallel architecture, the complexity is not higher than that of a conventional FIR filter of L g coefficients. The use of parallel implementation is mandatory in high-speed digital communications where parallelism factors on the order of 128 or higher are typical [22]. If the parallelism factor P is a multiple of the PTVE period, i.e.…”

“…The possibility of operating with a low sampling frequency, eliminating the need to use TI converters, also has the advantage of eliminating possible conversion errors inherent to that architecture (see. [22] for a detailed list of errors.). On the other hand, the same single converter can be used to sample the four electrical transmission channels (HI, HQ, VI, VQ) present in DP-QAM systems (see Fig.…”

Adaptive Digital Compensation of Analog Impairments in Frequency Interleaved ADC for Next-Generation High-Speed Communication Receivers

“…T HE demand for greater speeds in next-generation optical networks is driving research towards higher bandwidth (>100GHz) and sampling rate (>200Gs/s) analog-todigital converters (ADCs) and digital-to-analog converters (DACs) [1]- [5]. Although Time Interleaved (TI) data converters are today the solution of choice in high-speed communications [6], [7], they will be insufficient to meet the high bandwidth (BW) requirements of optical communications and other high-speed applications. Frequency Interleaved ADCs (FI-ADCs) have emerged as a promising solution to overcome the bandwidth limitations in high-speed digital communication receivers [8].…”

“…Overcoming these challenges is crucial to ensure optimal performance and maximize the benefits of FI-ADC technology in highspeed digital receivers. The compensation of impairments has been well studied for TI-ADC [7], [11], [12], as well as in architectures that include an in-phase/quadrature direct downconversion prior to the TI-ADC [13] 1 , which is used in RF applications. However, only a few articles in the past literature investigate the compensation of impairments in FI-ADCs (e.g., [14]- [20]).…”

“…To make FI-ADCs suitable for high-volume manufacturing of high-speed digital communication transceivers, the compensation algorithms should satisfy the following critical requirements [7]:…”