Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique

Han, Liang; Mishra, Piyush; Wu, Kaijie

doi:10.1109/tc.2007.27

Cited by 9 publications

(2 citation statements)

References 37 publications

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“…However there is no commercial automatic RHBD at RTL tool available. In [11], an SEU error correction method is proposed in which the data-paths are duplicated and the outputs of every stage are monitored continuously. In the case of a mismatch at each stage, second computation is triggered on one of the two data path while the other data path continues processing the next input.…”

Section: ) Rhbd At Register Transfer Levelmentioning

confidence: 99%

Radiation hardening by design: A novel gate level approach

Ghahroodi

Zwoliński

Özer

2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Soft errors induced by radiation, causing malfunctions in electronic systems and circuits, have become one of the most challenging issues that impact the reliability of the modern processors even in sea-level applications. In this paper we present two novel radiation-hardening techniques at Gate-level. We present a Single-Event-Upset (SEU) tolerant Flip-Flop design with 38% less power overhead and 25% less area overhead at 65nm technology comparing to the conventional Triple Modular Redundancy (TMR) for Flip-Flop design. We also present an SEU-tolerant Clock-Gating scheme with less than 50% areapower overheads and no performance penalty comparing to the conventional TMR for clock-gating. Our simulations show that the proposed schemes can recover from SEU errors in 99% of the cases.

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Section: ) Rhbd At Register Transfer Levelmentioning

confidence: 99%

Radiation hardening by design: A novel gate level approach

Ghahroodi

Zwoliński

Özer

2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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“…A recent survey on circuit/logic level CED techniques can be found at [18]. Recently, many CED techniques that exploit RT level scheduling and binding are proposed to achieve better CED capability with less overhead [13][14] [19][20] [21]. RT-level CED techniques use either space redundancy, or time redundancy, or both (hybrid redundancy).…”

Section: Fault Tolerancementioning

confidence: 99%

An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level

Liu

2009

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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As the integration level and clock speed of VLSI devices keep rising, power consumption of those devices increases dramatically. At the same time, shrinking size of transistors that enables denser and smaller chips running at faster clock speeds makes devices more susceptible to environment-induced faults. Both power reduction and concurrent error detection are becoming enabling technologies in Very Deep Sub Micron and nanometer technology domains. However, existing techniques either minimize power of "fault-free" devices, or improve fault tolerance without concerning power. Little work has been proposed to optimize the two objectives simultaneously. In this paper we attack this problem by unifying power efficiency and fault tolerance in a comprehensive Integer Linear Programming formulation. The proposed approach is tested using known benchmarks. MotivationOver the past decades significant technological progress has been made in Very Deep Sub-Micron (VDSM) and nanometer technology domains. However, the performance improvement due to shrinking size of transistors that enables denser and smaller chips running at faster clock speeds and consuming less power has come at the cost of decreased reliability, as warned by the International Technology Roadmap of Semiconductors (ITRS). Besides inherent design defects such as ground bounce, IR drop, leakage, and charge sharing, densely packed chips are also highly susceptible to environment-induced Single Event Upsets (SEU) and Single Event Latchups (SEL). To compensate for the inevitable increase of failures, and to avoid revenue losses, yield reduction, and time-to-market slowdown, the ITRS urges "automatic insertion of robustness into the design." On the other hand, design for power efficiency is now a domain under intensive research due to increased chip density and clock frequency. Power reduction techniques can help reduce power dissipation, extend battery lifetime, improve noise margin, and reduce packaging and cooling cost.However, until recently little research has been done to jointly consider both fault tolerance and power efficiency. This is mainly due to the direct conflict between the two objectives, as fault tolerance is usually achieved through redundancy (space, time, or information), and a redundant system unavoidably consumes more power than its non-redundant version. This conflict must be addressed properly since the need for power efficiency and fault tolerance continues rising while the demand for faster and better systems never stops. However, since the techniques for the two design objectives are developed independently, they inevitably achieve one but fail the other. For example, exploiting Register-Transfer (RT) level operation-to-cycle schedule and operation-to-unit binding to reduce switching activities will tend to disturb the schedule and binding tuned for fault detection, and vice versa. Further, the existing power-reduction techniques do not exploit the unique characteristics of faults and redundant computations, and will not result in good q...

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