Error Correction Schemes with Erasure Information for Fast Memories

Evain, Samuel; Savin, Valentin; Gherman, Valentin

doi:10.1007/s10836-014-5440-1

Cited by 2 publications

(9 citation statements)

References 18 publications

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“…Furthermore, ECC can be employed to correct errors with known locations. These types of errors are called erasures [Evain et al, 2014]. The concept of potentially-erroneous bits with recognized locations is well-known and is employed in digital communications but amazingly not commonly used in memory systems [Evain et al, 2014].…”

Section: Failure-aware Ecc Based Correctionmentioning

confidence: 99%

“…These types of errors are called erasures [Evain et al, 2014]. The concept of potentially-erroneous bits with recognized locations is well-known and is employed in digital communications but amazingly not commonly used in memory systems [Evain et al, 2014]. Theoretically, a code with minimum Hamming distance d can correct t random errors and r erasures if d>2*t+r [Walker et al, 1979;Carter et al, 1976;Siewiorek et al, 1998;Chen et al, 1984;Evain et al, 2014;N.…”

Section: Failure-aware Ecc Based Correctionmentioning

confidence: 99%

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Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC

Pajouhi

Fong

Raghunathan

et al. 2016

J. Emerg. Technol. Comput. Syst.

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Spin-Transfer Torque MRAMs are attractive due to their non-volatility, high density and zero leakage. However, STT-MRAMs suffer from poor reliability due to shared read and write paths. Additionally, conflicting requirements for data retention and write-ability (both related to the energy barrier height of the storage device) makes design more challenging. Furthermore, the energy barrier height depends on the geometry of the storage. Any variations in the geometry of the storage device lead to variations in the energy barrier height. In order to address poor reliability of STT-MRAMs, usage of Error Correcting Codes (ECC) has been proposed. Unlike traditional CMOS memory technologies, ECC is expected to correct both soft and hard errors in STT-MRAMs. To achieve acceptable yield with low write power, stronger ECC is required, resulting in increased number of encoded bits and degraded memory capacity. In this paper, we propose Failure-aware ECC (FaECC), which masks permanent faults while maintaining the same correction capability for soft errors without increased number of encoded bits. Furthermore, we investigate the impact of process variations on run-time reliability of STT-MRAMs. In order to analyze the effectiveness of our methodology, we developed a cross-layer simulation framework that consists of device, circuit and array level analysis of STT-MRAM memory arrays. Our results show that using FaECC relaxes the requirements on the energy barrier height, which reduces the write energy and results in smaller access transistor size and memory array area.

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Section: Failure-aware Ecc Based Correctionmentioning

confidence: 99%

Section: Failure-aware Ecc Based Correctionmentioning

confidence: 99%

Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC

Pajouhi

Fong

Raghunathan

et al. 2016

J. Emerg. Technol. Comput. Syst.

View full text Add to dashboard Cite

show abstract

“…This challenge can be addressed by promoting the detection and exploitation of weak bits, i.e., bits that are susceptible to be erroneously sensed, in order to improve the error correction capability of a conventional ECC decoder [1][4] [10]. Fully unreliable weak bits which offer no hint about their original program value are known as erasures [2][5] [8][9] [13] [18].…”

Section: Introductionmentioning

confidence: 99%

“…A way to identify weak bits in resistive and flash memories is to perform multiple sense operations with different reference values [8] [11][17] [19]. The resulting information can be considered as a rudimentary type of the soft-information [1][4] [10] usually used to boost the error correction capability of powerful ECCs such as low-density parity-check (LDPC) codes [16] [17] [19].…”

Section: Introductionmentioning

confidence: 99%

“…The considered procedure is to look for weak bits only upon indication of an uncorrectable error in a sensed memory word. Once identified, the weak bits are flipped and error correction is resumed [8] [11]. It is shown and formally proven that a conventional errors-only decoder reinforced with weak-bit-flipping becomes at least as efficient as an erasures-and-errors or a theoretical generalized-minimumdistance decoder [9] [10] if the goal is to correct up to i+1 erroneous bits per code word.…”

Section: Introductionmentioning

confidence: 99%

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