Error correction techniques for high-performance differential A/D converters

Tan, Khen-Sang; Kiriaki, S.; Wit, M. de; Fattaruso, J.W.; Tsay, C.-Y.; Matthews, W.E.; Hester, R.K.

doi:10.1109/4.62175

Cited by 64 publications

(30 citation statements)

References 6 publications

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“…Both analog calibration and digital error correction have been proposed to deal with the mismatch problem: the former uses additional capacitor banks to calibrate the capacitors in the foreground [37]; the latter utilizes equalization techniques to extract the exact weights of the capacitive array in the background [38,39]. With these methods, the matching requirement in the capacitive array becomes more relaxed but at the cost of design complexity.…”

Section: Capacitive Dacmentioning

confidence: 99%

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Zhang

2014

Linköping Studies in Science and Technology. Dissertations

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Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters(ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successive-approximation-register (SAR) ADC exhibits significantly high energy efficiency due to its good trade-offs among power consumption, conversion accuracy, and design complexity. This thesis examines the physical limitations and investigates the design methodologies and circuit techniques for low-speed and ultra-low-power SAR ADCs.The power consumption of SAR ADC is analyzed and its lower bounds are formulated in the thesis. At low resolutions, power is bounded by minimum feature sizes; while at medium to high resolutions, power is bounded by thermal noise and capacitor mismatch. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity for high resolution, a bottom-up weight calibration technique is further proposed. It utilizes redundancy generated by a non-binary-weighted capacitive network, and measures the actual weights of more significant capacitors using less significant capacitors.Three SAR ADCs have been implemented. The first ADC, fabricated in a 0.13µm CMOS process, achieves 9.1ENOB with 53-nW power consumption at 1kS/s. The main key to achieve the ultra-low-power operation turns out to be the maximal simplicity in the ADC architecture and low transistor count. In addition, a dual-supply voltage scheme allows the SAR digital logic to operate at 0.4V, reducing the overall power consumption of the ADC by 15% without any loss in performance. Based on the understanding from the first ADC and motivated by the predicted power bounds, the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process has been further fabricated. It achieves a substantial (94%) improvement in power consumption with 3-nW total power at 1kS/s and 0.7V. Following the same concept of imposing maximal simplicity in the ADC architecture and taking advantage of the smaller feature size, the ultra-low-power consumption is achieved by a matched splitiv array capacitive DAC, a bottom-plate full-range input-sampling scheme, a latch-based SAR control logic, and a multi-V T design approach. The third ADC fabricated in 65nm CMOS process targets at a higher resolution of 14b and a wider bandwidth of 5KHz. It achieves 12.5ENOB with 1.98-µW power consumption at 0.8V and 10kS/s. To achieve the high resolution, the ADC implements a uniform-geometry non-binaryweighted capacitive DAC and employs a secondary-bit approach to dynamically shift decision levels for error correction. Moreover, a comparator with bias control utilizes the redundancy to reduce the power consumption....

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Section: Capacitive Dacmentioning

confidence: 99%

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Zhang

2014

Linköping Studies in Science and Technology. Dissertations

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“…The ADC architecture of the fully differential successive approximation switched capacitor ADC [4,8] is widely used including two capacitor arrays, a fully differential buffer, a fully differential comparator with offset cancellation, a successive approximation register (SAR), and a control logic [1,2]. Various possible structures to realize the track-and-hold function exist in [3,4].…”

Section: Conventional Adc Architecturementioning

confidence: 99%

“…Analog-to-digital conversion can be accomplished in numerous ways, but apart from flash converters, only successive approximation methods of analog-to-digital conversion (ADC) are well known for producing accurate, medium speed conversion of analog signals [1][2][3][4][5][6]. It is a feedback scheme that uses a trial-and-error technique to approximate each analog sample with a corresponding digital word.…”

Section: Introductionmentioning

confidence: 99%

A 1.8-V 3.1 mW successive approximation ADC in system-on-chip

Shanli

Xia

et al. 2008

Analog Integr Circ Sig Process

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This paper describes a 10-bit 2.5 Msample/s successive approximation analog-to-digital converter (ADC) for SoC system. Based on conventional successive approximation ADC architecture a new and faster solution is used. The new solution consists of bootstrap switch, capacitors for sample-hold (S/H) circuit and DAC, using an offset cancellation method and there is no need for any active element. Together with an added bit and an offset compensation comparator the speed and accuracy is increased. The ADC exhibits higher 9 effective number of bits (ENOB) for sample rate to 2.5 Ms/s. The ADC consumes 3.1 mW from a 1.8 V supply and occupies about 0.25 mm 2 . The measured SNR is 56.05 dB.

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“…Charge redistribution successive approximation ADC's can achieve 18 bit resolution at 50kHz when self calibration techniques are used to overcome the matching problems of on chip capacitors [3,4]. The combination of resolution and speed is achieved by performing one comparison per bit (for an 18 bit conversion, the comparator must settle 18 times).…”

Section: Architecturementioning

confidence: 99%

“…24K, int n -3)(n -2)(n - (4) The last term of equation 4 can again be considered to be a residue, which is not accounted for by the digital outputs, the smaller the residue, the higher the resolution. The decrease of the residue as n increases is now on the order of n~4, which explains why the fourth order ADC is so much faster than the first order ADC.…”

Section: Fourth Order Incremental Adcmentioning

confidence: 99%