Error Detection Architectures for Ring Polynomial Multiplication and Modular Reduction of Ring-LWE in $\boldsymbol{\frac{\mathbb{Z}/p\mathbb{Z}[x]}{x^{n}+1}}$ Benchmarked on ASIC

Sarker, Ausmita; Kermani, Mehran Mozaffari; Azarderakhsh, Reza

doi:10.1109/tr.2020.2991671

Cited by 24 publications

(4 citation statements)

References 29 publications

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“…Broadcast routing is a straightforward method of flooding messages with other vehicles in groups. This procedure ensures that the message is delivered to all vehicles (Sarker et al, 2020;Kermani and Azarderakhsh, 2018). Flooding ensures packet delivery by ensuring that every node in the network receives the packet.…”

Section: B Broadcast-based Routingmentioning

confidence: 99%

Efficient Detection and Mitigation of Rushing Attacks in VANETs Using RAID: A Novel Intrusion Detection System

Kapu,

Karri

2023

Journal of Computer Science

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The vehicle manufacturing hub has evolved over the last decade with the emergence of self-driving vehicles and human-driven vehicles that use the concept of Artificial Intelligence (AI). Vehicular Ad Hoc Network (VANET) is a subset of Mobile Ad Hoc Network (MANET) that allows vehicles to communicate with one another and the Road Side Unit (RSU). VANET has been a game changer with features such as accident prevention, real-time traffic, route predictions, discovering an alternate route, alert notifications, safety, and security. VANET systems are distinguished by their ability to transmit critical safety information in real-time, even when the network's topology is constantly changing. With the lifesaving features of VANET comes a disadvantage that can risk the drivers' security and privacy through various attacks on the network. Intruders can steal data, drop data packets and modify, insert, or delete data when it is transmitted between vehicles. To address the mentioned data communication issues as well as various attacks in the VANET network, the authors propose an Intrusion Detection System (IDS) Rushing Attack Intrusion Detection (RAID), a novel framework that performs the detection of rushing attacks in vehicular networks. According to the performance analysis, the proposed framework RAID meets a wide range of security requirements while requiring less communication and storage. The study's findings were found to be more efficient.

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Section: B Broadcast-based Routingmentioning

confidence: 99%

Efficient Detection and Mitigation of Rushing Attacks in VANETs Using RAID: A Novel Intrusion Detection System

Kapu,

Karri

2023

Journal of Computer Science

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“…For sensitive systems, degraded performance can lead to disastrous results; consequently, research has explored strategies to reduce errors and provide higher reliability with acceptable overhead [16,17,18,19,20,21,22,23,24]. In [16], a ingerprint-based technique for detecting malicious programs in hardware is presented.…”

Section: Previous Workmentioning

confidence: 99%

“…In [18] and [19], fault detection mechanisms are presented for the lightweight cryptographic block cipher QARMA and polynomial basis inversions, respectively. Moreover, error detection constructions based on recomputation with encoded (shifted) operands and recomputation with encoded (negated) operands for the Ring-LWE and for the ring polynomial multiplication and modular reduction of Ring-LWE are implemented in [20] and [21], respectively. Lastly, error detection schemes are proposed for secure cryptographic GCM structures in [22], for Hash-Counter-Hash tweakable enciphering constructions in [23], and for cryptographic applications using multipliers in [24].…”

Section: Previous Workmentioning

confidence: 99%

Reliable Constructions for the Key Generator of Code-based Post-quantum Cryptosystems on FPGA

Canto

Kermani

Azarderakhsh

2022

J. Emerg. Technol. Comput. Syst.

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Advances in quantum computing have urged the need for cryptographic algorithms which are low-power, low-energy, and secure against attacks that can be potentially enabled. For this post-quantum age, different solutions have been studied. Code-based cryptography is one feasible solution whose hardware architectures have become the focus of research in the NIST standardization process and has been advanced to the final round (to be concluded by 2022-2024). Nevertheless, although these constructions, e.g., McEliece and Niederreiter public key cryptography, have strong error correction properties, previous studies have proved the vulnerability of their hardware implementations against faults product of the environment and intentional faults, i.e., differential fault analysis (DFA). It is previously shown that depending on the codes used, i.e., classical or reduced (using either quasi-dyadic Goppa codes or quasi-cyclic alternant codes), flaws in error detection could be observed. In this work, efficient fault detection constructions are proposed for the first time to account for such shortcomings. Such schemes are based on regular parity, interleaved parity, and two different cyclic redundancy checks (CRC), i.e., CRC-2 and CRC-8. Without losing the generality, we experiment on the McEliece variant, noting that the presented schemes can be used for other code-based cryptosystems. We perform error detection capability assessments and implementations on field-programmable gate array (FPGA) Kintex-7 device xc7k70tfbv676-1 to verify the practicality of the presented approaches. To demonstrate the appropriateness for constrained embedded systems, the performance degradation and overheads of the presented schemes are assessed.

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“…Moving on, Anastasova et al [37] explore the fast strategies for the implementation of Supersingular Isogeny Key Encapsulation (SIKE) Round 3 on ARM Cortex-M4, showcasing optimized techniques. Additionally, [38] discusses error detection architectures for Ring Polynomial Multiplication and Modular Reduction of Ring-LWE, providing valuable insights into ASIC implementations. These works collectively contribute to the advancement of cryptographic implementations on resource-constrained platforms and are crucial in the context of secure and reliable systems.…”

Section: Introductionmentioning

confidence: 99%

Flexible and Parallel Architectures for Optimal Ate pairing on FPGA

Oussama

Akil

Koudil

et al. 2022

Preprint

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This paper presents three approaches for the implementation of Optimal Ate pairing based on Jacobean coordinates, over Barreto-Naehrig curves, targeting the 128 bits security level, in Genesys board. The first approach is a fully software implementation using MicroBlaze processor. The second approach is software/hardware implementation, in which the most useful operations in ${\varvec{F}}_{\varvec{p}}$ and ${\varvec{F}}_{{\varvec{p}}^{2}}$ are coded as intellectual property cores around the Microblaze. The third approach is based on the second in which we exploit the parallelism that exists to compute Optimal Ate pairing. The integration of multi-MicroBlaze processor in single architecture allows not only the flexibility of the overall system but also the parallelism to speed up pairing. Various techniques and parameters are used and combined to compute Optimal Ate in efficient way, namely: Montgomery modular multiplication, Karatsuba method, Jacobean coordinate, Complex method for squaring, Sparse multiplication, squaring in the cyclotomic subgroup ${\varvec{G}}_{\varvec{\varphi }6}\left({\varvec{F}}_{{\varvec{p}}^{12}}\right)$ and addition chain method. Our flexible and parallel systems are dedicated for restricted environment resources with a reasonable execution time.

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Error Detection Architectures for Ring Polynomial Multiplication and Modular Reduction of Ring-LWE in $\boldsymbol{\frac{\mathbb{Z}/p\mathbb{Z}[x]}{x^{n}+1}}$ Benchmarked on ASIC

Cited by 24 publications

References 29 publications

Efficient Detection and Mitigation of Rushing Attacks in VANETs Using RAID: A Novel Intrusion Detection System

Efficient Detection and Mitigation of Rushing Attacks in VANETs Using RAID: A Novel Intrusion Detection System

Reliable Constructions for the Key Generator of Code-based Post-quantum Cryptosystems on FPGA

Flexible and Parallel Architectures for Optimal Ate pairing on FPGA

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