Escape Routing for Staggered-Pin-Array PCBs

Ho, Yuan-Kai; Lee, Hsu-Chieh; Chang, Yao-Wen

doi:10.1109/tcad.2013.2259539

Cited by 11 publications

(1 citation statement)

References 21 publications

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“…There are studies that only consider escape routing (McDaniel, Grissom & Brisk, 2014) while, there are some studies which consider other problems like length matching (Zhang et al, 2015b, Yan, 2015, Chang, Wen & Chang, 2019 along with the escape routing as well. Some have used staggered pin array (Ho, Lee & Chang, 2013; while others have used grid pin array (Jiao & Dong, 2016) as well. Apart from electrical circuits, escape routing is also used for designing micro-fluid biochips PCBs (McDaniel et al, 2016).…”

Section: Related Workmentioning

confidence: 99%

A dual model node based optimization algorithm for simultaneous escape routing in PCBs

Ali

Anjum

Zeeshan

2021

PeerJ Computer Science

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Simultaneous Escape Routing (SER) is the escaping of circuit pins simultaneously from inside two or more pin arrays. This is comparatively difficult as compared to routing in a single array and has not been addressed by previous studies. The increase in pin array complexity has made the manual SER in PCBs a very inefficient and tedious task and there surely is need for the automated routing algorithms. In this work, we propose network flow based optimal algorithm that uses integer linear program to solve SER problem and area routing problem in two stages. In the first stage, pins are escaped to the boundaries of pin arrays simultaneously. These escaped pins are connected with each other in the second stage. The proposed algorithm is tested for different benchmark sizes of grids and the results show that it is not only better in terms of routability but also outperforms existing state of the art algorithms in terms of time consumption. The existing algorithms either fails to achieve higher routability or have larger time complexities, whereas the proposed algorithm achieves 99.9% routability and is also independent of grid topology and component pin arrangement, which shows the superiority of proposed algorithm over the existing algorithms.

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