ESD Evaluation of the Emerging MuGFET Technology

Ruß, Christian; Gossner, Harald; Schulz, T.; Chaudhary, Nirmal; Xiong, Wenjing; Marshall, Andrew; Duvvury, C.; Schrüfer, K.; Cleavelin, C.R.

doi:10.1109/tdmr.2006.888288

Cited by 12 publications

(4 citation statements)

References 8 publications

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“…The thermal behavior is already a concern in MOS operation, but even more under ESD conditions exhibiting 1-2 orders of magnitude higher current density. Very low ESD failure thresholds have been reported in MugFET technologies [2]. The critical current density Novel Devices in ESD Protection H. Gossner It2, at which damage occurs, has been detected as low as a few µA.…”

Section: A Devicementioning

confidence: 99%

“…In the case of MugFETs the isolation of the body region from the substrate impacts the electro-thermal behavior seriously. Especially high current densities which are typical for ESD events immediately generate excess temperature which destroys the device [2], [3]. The mechanism and an optimization strategy will be discussed in chapter 2 and 3.…”

Section: Introductionmentioning

confidence: 99%

“…: a) schematic view of a single fin MugFET b)SEM micrograph of a multi-fin structure c) schematic cross section of a fin[2].…”

mentioning

confidence: 99%

“…A current pulse of 0.5 mA is forced through the single fin (equivalent to 10 mA/µm in bulk Si). The temperature distribution [K] after 100 ns is depicted [Pulsed IV characteristic of a) grounded gate planar SOI NFET (W=50µm)[2], b) grounded gate FINFET (bipolar) and FINFET operated as MOS-diode for different gate lengths[4]. The FINFET devices have a fin width of 30nm, 145nm fin spacing and 400 fins in parallel.…”

mentioning

confidence: 99%

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Novel devices in ESD protection

Gossner

Schneider

2007

2007 International Workshop on Physics of Semiconductor Devices

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ESD protection circuits are part of any electronic circuit to ensure robustness against electrical surges. The choice of the ESD protection concept strongly depends on the IO devices. The integration of devices like DeMOS for high voltage interfaces in system on chip applications and multigate FETs in advanced CMOS requires new process optimization strategies taking into account the high current behavior of these devices. The specific thermal behavior of fin structures and the base push out in DeMOS devices during an ESD event are found to be detrimental. However, by the presented process and design modifications the initially very low ESD robustness of < 0.1 mA/µm can be raised to levels which are compliant with IC design constraints.

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Section: A Devicementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…: a) schematic view of a single fin MugFET b)SEM micrograph of a multi-fin structure c) schematic cross section of a fin[2].…”

mentioning

confidence: 99%

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confidence: 99%

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