“…1, a complete fullchip ESD protection scheme requires multiple ESD devices per pad to discharge ESD surges with different polarities, i.e., positive from I/O to V SS (PS), negative from I/O to V SS (NS), positive from I/O to V DD (PD), negative from I/O to V DD (ND), positive from V DD to V SS (DS) and positive from V SS to V DD (SD). There are several ESD design challenges [6][7][8]. The first one is ESD design optimization and prediction, which requires comprehensive mixed-mode ESD simulation to address the complex coupling effects among electrothermal, process, device, circuit and layout.…”