ESR of interfaces and nanolayers in semiconductor heterostructures

Stesmans, André; Afanas’ev, Valery V.

doi:10.1016/b978-0-444-53099-8.00013-0

Cited by 11 publications

(5 citation statements)

References 162 publications

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“…5(b)] suggest that the same bond breaking process at the Si/SiO 2 interface, i.e., the de-passivation of H-passivated Si dangling bonds (Pb 0 ), is likely to be taking place also in (Si)Ge devices. We have previously reported [12] Electron Spin Resonance Spectroscopy (ESR) [29] measurements on a Ge substrate with a thick Si cap which revealed a high Pb 0 density (∼1 × 10 12 cm −2 ), while these defects could not be detected (< 10 11 cm −2 ) on a very thin Si cap. This observation suggests that the Ge segregation at the Si/SiO 2 interface reported for Ge-based channels and enhanced by the use of a Si cap with reduced Si cap thickness [30] can reduce the N it precursor defect density (Si-H bonds) and therefore the ΔN it during NBTI stress.…”

Section: Modelmentioning

confidence: 93%

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Franco

Kaczer

Mitard

et al. 2013

IEEE Trans. Device Mater. Relib.

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Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a SiO 2 /HfO 2 dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups.

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Section: Modelmentioning

confidence: 93%

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Franco

Kaczer

Mitard

et al. 2013

IEEE Trans. Device Mater. Relib.

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“…The passivation of P b0 defects is pictured as the formation of P b0 -H bonds (see eq. ( 1)), but, as outlined previously [11,26] at (a) Ref. [12].…”

mentioning

confidence: 88%

“…Paramagnetic defects at the macroscopic planar Si/SiO 2 interfaces (see, e.g., ref. [11] and references therein) have been intensively studied and their understanding has proven crucial for the technological advancement of the Si-based electronic devices. In the case of the onedimensional (1D) Si NWs the interfaces/borders play an overwhelming role [2] where occurring defects (mainly Si DBs) take a key position in (re)distributing stress at the interfaces.…”

mentioning

confidence: 99%

“…As outlined above, experimental tracking of the passivation behavior of the P NW b0 defects beyond the T an > 403 • C range has failed because of ESR sensitivity reasons. Yet, along previous insight [11,26], one might attempt, based on the assembled, albeit limited, set of data, to make a prognosis for the optimal achievable level of P NW b0 -defect inactivation at the Si NW/SiO 2 interfaces. The passivation of P b0 defects is pictured as the formation of P b0 -H bonds (see eq.…”

mentioning

confidence: 99%

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Functionality of thermally hydrogen-passivated interfaces of oxidized crystalline arrays of Si nanowires on (100)Si

Jivānescu¹,

Stesmans²,

Kurstjens³

2014

EPL

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Electron spin resonance studies have been performed on arrays of single-crystalline Si nanowires (NWs), 375 nm long and of top diameter of about 5 nm, fabricated on (100)Si by topdown etching and final thinning by thermal oxidation in dry O2/N2 at 1150 • C. The SiO2/SiNW interfaces, showing a density of inherent electrically detrimental P b0 (Si3 ≡ Si • ) defects substantially exceeding that of standard technological (100)Si/SiO2, are of inferior electrical quality. An extensive study of the passivation kinetics in H2 and forming gas ambient reveals that, even under optimized conditions, the defect system cannot be inactivated to device grade (at best, 40× improvement in H2), due to the excessive interface stress as exposed by the enhanced spread in activation energy for hydrogen passivation kinetics. The data reveal the inability, of intrinsic nature, to sufficiently suppress P b0 defects, preventing to reach device-grade functioning of solar cells using single-crystalline NW arrays on (100)Si in the current state of manufacturing.

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“…N it creation during NBTI stress is commonly attributed to de-passivation of Hpassivated Si dangling bonds (P b0 ) at the Si/SiO 2 interface. We have previously reported (13) Electron Spin Resonance Spectroscopy (ESR) (31) measured on a Ge substrate with a thick Si cap which revealed a high P b0 density (~1x10 12 cm -2 ) while it could not detect these defects (<10 11 cm -2 ) for a very thin Si cap. This suggested that the higher Ge segregation at the Si/SiO 2 interface reported for thin Si caps (32) can reduce the N it precursor defect density and therefore reduce ΔN it during NBTI stress.…”

Section: Reduced Permanent Component Of Nbti (δN It )mentioning

confidence: 99%

(Invited) Reliability of SiGe Channel MOS

Franco¹,

Kaczer²,

Mitard³

et al. 2013

ECS Trans.

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We report extensive experimental results on the Negative Bias Temperature Instability (NBTI) of SiGe channel pMOSFETs as a function of the main gate stack parameters. These results clearly show that this high-mobility channel technology offers a significantly improved NBTI robustness compared to Si-channel devices, which can virtually eliminate this critical reliability issue for sub-1 nm EOT devices. The intrinsically superior NBTI robustness is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. Thanks to this effect, both a significantly reduced time-dependent variability in nanoscaled SiGe devices and a reduced low-frequency noise are also observed. Other reliability mechanisms, such as Channel Hot Carriers and Time-Dependent Dielectric Breakdown are shown not to be showstoppers. All these aspects underscore the SiGe channel technology as a very promising alternative to Si pMOSFETs for future CMOS technology nodes.

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ESR of interfaces and nanolayers in semiconductor heterostructures

Cited by 11 publications

References 162 publications

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Functionality of thermally hydrogen-passivated interfaces of oxidized crystalline arrays of Si nanowires on (100)Si

(Invited) Reliability of SiGe Channel MOS

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